[PATCH] arm64: dts: ti: k3-am642-evm: Add onboard clock overlay for PCIe and SERDES

[Siddharth Vadapalli]

On certain variants of the AM642 EVMs, there is an onboard clock generator
named 'PCIe Clock HCSL (100MHz)' that outputs two 100 MHz differential
clock pair signals:
- One differential clock pair signal is fed to the PCIe Connector to serve
  as the PCIe reference clock output.
- The other differential clock pair signal is input to the SERDES as the
  reference clock for the SERDES.

In such a configuration, the SERDES should not output the PCIe reference
clock (avoid clock contention), and, the SERDES should use the onboard
clock generator as its reference clock.

Add a device-tree overlay to enable this.

Co-developed-by: Bin Liu <b-liu at ti.com>
Signed-off-by: Bin Liu <b-liu at ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli at ti.com>
---

Hello,

This patch is based on linux-next tagged next-20251024.

Patch has been tested on an AM642-EVM variant that has the onboard clock
generator by applying the device-tree overlay at the Bootloader stage to
update the device-tree file 'k3-am642-evm.dtb'. An NVMe SSD was connected
to the PCIe Connector and the NVMe SSD has been verified to be functional
implying that both PCIe and SERDES are functional.
Test Logs:
https://gist.github.com/Siddharth-Vadapalli-at-TI/1ca4c28d7db5a0ee3f884508dd2aa348

Regards,
Siddharth.

 arch/arm64/boot/dts/ti/Makefile               |  4 ++
 ...-am642-evm-onboard-clkgen-pcie-serdes.dtso | 38 +++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm-onboard-clkgen-pcie-serdes.dtso

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 743115b849a7..bdc1307cac90 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-onboard-clkgen-pcie-serdes.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-pcie0-ep.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-pcie.dtb
@@ -194,6 +195,8 @@ k3-am642-evm-icssg1-dualemac-dtbs := \
 	k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo
 k3-am642-evm-icssg1-dualemac-mii-dtbs := \
 	k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac-mii.dtbo
+k3-am642-evm-onboard-clkgen-pcie-serdes-dtbs := \
+	k3-am642-evm.dtb k3-am642-evm-onboard-clkgen-pcie-serdes.dtbo
 k3-am642-evm-pcie0-ep-dtbs := \
 	k3-am642-evm.dtb k3-am642-evm-pcie0-ep.dtbo
 k3-am642-phyboard-electra-disable-eth-phy-dtbs := \
@@ -267,6 +270,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
 	k3-am62p5-sk-csi2-tevi-ov5640.dtb \
 	k3-am642-evm-icssg1-dualemac.dtb \
 	k3-am642-evm-icssg1-dualemac-mii.dtb \
+	k3-am642-evm-onboard-clkgen-pcie-serdes.dtb \
 	k3-am642-evm-pcie0-ep.dtb \
 	k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \
 	k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-onboard-clkgen-pcie-serdes.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-onboard-clkgen-pcie-serdes.dtso
new file mode 100644
index 000000000000..d04c92033c7b
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm-onboard-clkgen-pcie-serdes.dtso
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for utilizing the "PCIe Clock HCSL (100MHz)" onboard clock
+ * generator. The clock generator outputs two 100 MHz differential clock
+ * pair signals for the purpose of:
+ * 1) Supplying the PCIe reference clock to the PCIe connector
+ * 2) Supplying the Reference clock to SERDES0
+ *
+ * AM642 EVM Product Link: https://www.ti.com/tool/TMDS64EVM
+ *
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/phy/phy-ti.h>
+
+/* Onboard clock generator provides 100 MHz reference clock to SERDES0 */
+&serdes_refclk {
+	clock-frequency = <100000000>;
+};
+
+&serdes0 {
+	/*
+	 * Remove 'phy_en_refclk' clock since SERDES0 doesn't have to generate the
+	 * PCIe reference clock (provided by the onboard clock generator).
+	 */
+	clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>;
+	clock-names = "refclk";
+	assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+			  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+			  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+	/* Use onboard clock generator as SERDES0 reference clock */
+	assigned-clock-parents = <&serdes_refclk>,
+				 <&serdes_refclk>,
+				 <&serdes_refclk>;
+};
-- 
2.51.0