[PATCH] arm64: guard AMU register access with ARM64_HAS_AMU_EXTN

[Marek Vasut]

The AMU configuration register access may fault and prevent successful
kernel boot. This can occur for example in case the firmware does not
allow AMU counter access from EL1. Guard the AMU configuration register
access with ARM64_HAS_AMU_EXTN to prevent this fault if ARM64_HAS_AMU_EXTN
Kconfig option is explicitly disabled. Other interaction with the AMU is
already guarded by similar ifdeffery.

Fixes: 87a1f063464a ("arm64: trap to EL1 accesses to AMU counters from EL0")
Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
---
Cc: Anshuman Khandual <anshuman.khandual at arm.com>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Geert Uytterhoeven <geert+renesas at glider.be>
Cc: Marc Zyngier <maz at kernel.org>
Cc: Ryan Roberts <ryan.roberts at arm.com>
Cc: Will Deacon <will at kernel.org>
Cc: Yicong Yang <yangyicong at hisilicon.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-renesas-soc at vger.kernel.org
---
 arch/arm64/mm/proc.S | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 86818511962b6..123538ffeda6b 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -145,7 +145,9 @@ SYM_FUNC_START(cpu_do_resume)
 	ubfx	x11, x11, #1, #1
 	msr	oslar_el1, x11
 	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
+alternative_if ARM64_HAS_AMU_EXTN
 	reset_amuserenr_el0 x0			// Disable AMU access from EL0
+alternative_else_nop_endif
 
 alternative_if ARM64_HAS_RAS_EXTN
 	msr_s	SYS_DISR_EL1, xzr
@@ -470,7 +472,9 @@ SYM_FUNC_START(__cpu_setup)
 	mov	x1, MDSCR_EL1_TDCC		// Reset mdscr_el1 and disable
 	msr	mdscr_el1, x1			// access to the DCC from EL0
 	reset_pmuserenr_el0 x1			// Disable PMU access from EL0
+alternative_if ARM64_HAS_AMU_EXTN
 	reset_amuserenr_el0 x1			// Disable AMU access from EL0
+alternative_else_nop_endif
 
 	/*
 	 * Default values for VMSA control registers. These will be adjusted
-- 
2.51.0