[boot-wrapper PATCH 1/4] aarch64: do not trap MPAM register accesses

[Andre Przywara]

The architectural MPAM system registers in lower ELs are controlled by
an EL3 control bit. To allow access to registers like MPAM2_EL2 or
MPAM_EL1, clear the TRAPLOWER bit in the MPAM3_EL3 system register, to
avoid an unhandled trap into the boot-wrapper code.

Signed-off-by: Andre Przywara <andre.przywara at arm.com>
---
 arch/aarch64/include/asm/cpu.h | 4 ++++
 arch/aarch64/init.c            | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index ac50474..0f6e2ce 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -29,6 +29,9 @@
 #define HFGWTR2_EL2		s3_4_c3_c1_3
 #define HFGITR2_EL2		s3_4_c3_c1_7
 
+#define MPAM3_EL3		s3_6_c10_c5_0
+#define MPAM3_EL3_TRAPLOWER	BIT(62)
+
 /*
  * RES1 bit definitions definitions as of ARM DDI 0487G.b
  *
@@ -120,6 +123,7 @@
 
 #define ID_AA64PFR0_EL1_RAS		BITS(31, 28)
 #define ID_AA64PFR0_EL1_SVE		BITS(35, 32)
+#define ID_AA64PFR0_EL1_MPAM		BITS(43, 40)
 #define ID_AA64PFR0_EL1_CSV2		BITS(59, 56)
 
 #define ID_AA64PFR1_EL1_MTE		BITS(11, 8)
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index cb24f4e..99e43cf 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -198,6 +198,9 @@ static void cpu_init_el3(void)
 
 		msr(SMCR_EL3, smcr);
 	}
+
+	if (mrs_field(ID_AA64PFR0_EL1, MPAM))
+		msr(MPAM3_EL3, mrs(MPAM3_EL3) & ~MPAM3_EL3_TRAPLOWER);
 }
 
 void cpu_init_el2_armv8r(void)
-- 
2.25.1