[PATCH 3/4] arm64: dts: imx8mp-phyboard-pollux: Enable i2c3

[Yannic Moog]

On Mon, 2025-10-20 at 11:38 -0400, Frank Li wrote:
> On Mon, Oct 20, 2025 at 03:11:24PM +0200, Yannic Moog wrote:
> > From: Stefan Riedmueller <s.riedmueller at phytec.de>
> > 
> > On the phyBOARD-Pollux the i2c3 node is used on the CSI1 interface to
> > connect to imaging sensors. Thus define it so it can be easily enabled if
> > required.
> Nit:
> 
> The i2c3 of the phyBOARD-Pollux is used ...

Sorry, I can't follow. Would you like me to rephrase the commit message?

Yannic

> 
> Reviewed-by: Frank Li <Frank.Li at nxp.com>
> 
> > 
> > Signed-off-by: Stefan Riedmueller <s.riedmueller at phytec.de>
> > Signed-off-by: Teresa Remmet <t.remmet at phytec.de>
> > Signed-off-by: Yannic Moog <y.moog at phytec.de>
> > ---
> >  .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts   | 23 ++++++++++++++++++++++
> >  1 file changed, 23 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> > index 6203e39bc01be476f16f5ac80b6365bce150ae37..7d34b820e3213a3832c5be47444d4e9c636a6202 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
> > @@ -228,6 +228,15 @@ led-3 {
> >  	};
> >  };
> > 
> > +&i2c3 {
> > +	clock-frequency = <400000>;
> > +	pinctrl-names = "default", "gpio";
> > +	pinctrl-0 = <&pinctrl_i2c3>;
> > +	pinctrl-1 = <&pinctrl_i2c3_gpio>;
> > +	sda-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > +	scl-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > +};
> > +
> >  &ldb_lvds_ch1 {
> >  	remote-endpoint = <&panel1_in>;
> >  };
> > @@ -442,6 +451,20 @@ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1e2
> >  		>;
> >  	};
> > 
> > +	pinctrl_i2c3: i2c3grp {
> > +		fsl,pins = <
> > +			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
> > +			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
> > +		>;
> > +	};
> > +
> > +	pinctrl_i2c3_gpio: i2c3gpiogrp {
> > +		fsl,pins = <
> > +			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x1e2
> > +			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x1e2
> > +		>;
> > +	};
> > +
> >  	pinctrl_lvds1: lvds1grp {
> >  		fsl,pins = <
> >  			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20		0x12
> > 
> > --
> > 2.51.0
> >