[PATCH v3 3/3] arm64: dts: renesas: r8a77961: Add GX6250 GPU node

[Marek Vasut]

Describe Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58
present in Renesas R-Car R8A77961 M3-W+ SoC.

Acked-by: Matt Coster <matt.coster at imgtec.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas at ragnatech.se>
Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
---
Cc: Adam Ford <aford173 at gmail.com>
Cc: Conor Dooley <conor+dt at kernel.org>
Cc: David Airlie <airlied at gmail.com>
Cc: Frank Binns <frank.binns at imgtec.com>
Cc: Geert Uytterhoeven <geert+renesas at glider.be>
Cc: Krzysztof Kozlowski <krzk+dt at kernel.org>
Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Matt Coster <matt.coster at imgtec.com>
Cc: Maxime Ripard <mripard at kernel.org>
Cc: Rob Herring <robh at kernel.org>
Cc: Simona Vetter <simona at ffwll.ch>
Cc: Thomas Zimmermann <tzimmermann at suse.de>
Cc: devicetree at vger.kernel.org
Cc: dri-devel at lists.freedesktop.org
Cc: linux-renesas-soc at vger.kernel.org
---
V2: - Add RB from Niklas
    - Fix up power-domains = <&sysc R8A77961_PD_3DG_B>; for 77961
    - Fill in all three clock and two power domains
V3: - Add AB from Matt
    - Disable the GPU by default
---
 arch/arm64/boot/dts/renesas/r8a77961.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
index 12435ad9adc04..31b11bdab69b9 100644
--- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
@@ -2455,6 +2455,23 @@ gic: interrupt-controller at f1010000 {
 			resets = <&cpg 408>;
 		};
 
+		gpu: gpu at fd000000 {
+			compatible = "renesas,r8a77961-gpu",
+				     "img,img-gx6250",
+				     "img,img-rogue";
+			reg = <0 0xfd000000 0 0x40000>;
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_CORE R8A77961_CLK_ZG>,
+				 <&cpg CPG_CORE R8A77961_CLK_S2D1>,
+				 <&cpg CPG_MOD 112>;
+			clock-names = "core", "mem", "sys";
+			power-domains = <&sysc R8A77961_PD_3DG_A>,
+					<&sysc R8A77961_PD_3DG_B>;
+			power-domain-names = "a", "b";
+			resets = <&cpg 112>;
+			status = "disabled";
+		};
+
 		pciec0: pcie at fe000000 {
 			compatible = "renesas,pcie-r8a77961",
 				     "renesas,pcie-rcar-gen3";
-- 
2.51.0