[PATCH 06/11] clk: sunxi-ng: sun55i-a523-ccu: Lower audio0 pll minimum rate
Jernej Škrabec
jernej.skrabec at gmail.com
Mon Oct 20 11:22:55 PDT 2025
Dne ponedeljek, 20. oktober 2025 ob 20:09:18 Srednjeevropski poletni čas je Chen-Yu Tsai napisal(a):
> On Tue, Oct 21, 2025 at 1:52 AM Jernej Škrabec <jernej.skrabec at gmail.com> wrote:
> >
> > Dne ponedeljek, 20. oktober 2025 ob 19:10:52 Srednjeevropski poletni čas je Chen-Yu Tsai napisal(a):
> > > While the user manual states that the PLL's rate should be between 180
> > > MHz and 3 GHz in the register defninition section, it also says the
> > > actual operating frequency is 22.5792*4 MHz in the PLL features table.
> > >
> > > 22.5792*4 MHz is one of the actual clock rates that we want and is
> > > is available in the SDM table. Lower the minimum clock rate to 90 MHz
> > > so that both rates in the SDM table can be used.
> >
> > So factor of 2 could be missed somewhere?
>
> Not sure what you mean? This PLL only gives *4 and *1 outputs.
Right. Nevermind then.
Best regards,
Jernej
>
> > >
> > > Fixes: 7cae1e2b5544 ("clk: sunxi-ng: Add support for the A523/T527 CCU PLLs")
> > > Signed-off-by: Chen-Yu Tsai <wens at kernel.org>
> >
> > Reviewed-by: Jernej Skrabec <jernej.skrabec at gmail.com>
> >
> > Best regards,
> > Jernej
> >
> > > ---
> > > drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
> > > index acb532f8361b..20dad06b37ca 100644
> > > --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
> > > +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
> > > @@ -300,7 +300,7 @@ static struct ccu_nm pll_audio0_4x_clk = {
> > > .m = _SUNXI_CCU_DIV(16, 6),
> > > .sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
> > > 0x178, BIT(31)),
> > > - .min_rate = 180000000U,
> > > + .min_rate = 90000000U,
> > > .max_rate = 3000000000U,
> > > .common = {
> > > .reg = 0x078,
> > >
> >
> >
> >
> >
>
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