[PATCH 29/39] dt-bindings: display: bridge: Document Freescale i.MX95 MIPI DSI

[Marek Vasut]

On 10/13/25 9:13 PM, Frank Li wrote:
> On Sat, Oct 11, 2025 at 06:51:44PM +0200, Marek Vasut wrote:
>> Freescale i.MX95 SoC embeds a Synopsys Designware MIPI DSI host
>> controller and a Synopsys Designware MIPI DPHY. Unlike the i.MX93
>> PHY, the i.MX95 PHY uses more syscon interfaces to configure the
>> PHY.
> 
> Any common driver for Synopsys Designware MIPI DSI, suppose many vendor
> use this IP?

Sure, the IP is common, the "glue logic" is SoC-specific.

>>   properties:
>>     compatible:
>> -    const: fsl,imx93-mipi-dsi
>> +    enum:
>> +      - fsl,imx93-mipi-dsi
>> +      - fsl,imx95-mipi-dsi
>>
>>     clocks:
>>       items:
>> @@ -46,13 +45,52 @@ properties:
>>         controller and MIPI DPHY PLL related configurations through PLL SoC
>>         interface.
>>
>> +  fsl,disp-master-csr:
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +    description:
>> +      i.MX95 Display Master CSR is a syscon which includes registers to
>> +      control DSI clock settings, clock gating, and pixel link select.
> 
> why not go through standard phy interface?
> 
>> +
>> +  fsl,disp-stream-csr:
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +    description:
>> +      i.MX95 Display Stream CSR is a syscon which includes configuration
>> +      and status registers for the DSI host.
> 
> why not go through standard phy interface?
These are aux control signals , these registers are not PHY .