[PATCH 25/39] dt-bindings: display: bridge: Document NXP i.MX95 pixel interleaver support

[Marek Vasut]

On 10/13/25 8:57 PM, Frank Li wrote:

Hello Frank,

>> +  fsl,syscon:
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +    description: |
>> +      A phandle which points to Control and Status Registers (CSR) module.
> 
> Need justify why not standard interface such as clock, phy, reset ...

Because this is neither clock, nor reset nor anything else. This is 
really only a remote register which controls the pixel interleaving. 
Therefore, syscon.

>> +
>> +  ports:
>> +    $ref: /schemas/graph.yaml#/properties/ports
>> +
>> +    properties:
>> +      port at 0:
>> +        $ref: /schemas/graph.yaml#/properties/port
> 
> video-interfaces.yaml?
No, because none of the properties in video-interfaces.yaml are 
applicable to this port as far as I can tell.

The rest is fixed, thanks !