[PATCH 2/3] arm64: dts: renesas: r8a77960: Add GX6250 GPU node

[Matt Coster]

On 13/10/2025 20:01, Marek Vasut wrote:
> Describe Imagination Technologies PowerVR Rogue GX6250 BNVC 4.45.2.58
> present in Renesas R-Car R8A77960 M3-W SoC.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
> ---
> Cc: Adam Ford <aford173 at gmail.com>
> Cc: Conor Dooley <conor+dt at kernel.org>
> Cc: David Airlie <airlied at gmail.com>
> Cc: Frank Binns <frank.binns at imgtec.com>
> Cc: Geert Uytterhoeven <geert+renesas at glider.be>
> Cc: Krzysztof Kozlowski <krzk+dt at kernel.org>
> Cc: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Cc: Matt Coster <matt.coster at imgtec.com>
> Cc: Maxime Ripard <mripard at kernel.org>
> Cc: Rob Herring <robh at kernel.org>
> Cc: Simona Vetter <simona at ffwll.ch>
> Cc: Thomas Zimmermann <tzimmermann at suse.de>
> Cc: devicetree at vger.kernel.org
> Cc: dri-devel at lists.freedesktop.org
> Cc: linux-renesas-soc at vger.kernel.org
> ---
>  arch/arm64/boot/dts/renesas/r8a77960.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
> index 6d039019905de..4f7b2e838c026 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
> @@ -2565,6 +2565,18 @@ gic: interrupt-controller at f1010000 {
>  			resets = <&cpg 408>;
>  		};
>  
> +		gpu: gpu at fd000000 {
> +			compatible = "renesas,r8a77960-gpu",
> +				     "img,img-gx6250",
> +				     "img,img-rogue";
> +			reg = <0 0xfd000000 0 0x40000>;
> +			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 112>;
> +			clock-names = "core";
> +			power-domains = <&sysc R8A7796_PD_3DG_B>;

My comments here apply to the other dts patch (P3/3) as well since the
integration appears to be identical between the two SoCs.

There are two power domains on this GPU and the SoC exposes both of
them; no reason to fall back to the single-domain scheme here.

I know the sysc driver declares the dependency of _B on _A, but the dts
shouldn't rely on that, so can we have:

   power-domains = <&sysc R8A7796_PD_3DG_A>, <&sysc R8A7796_PD_3DG_B>;
   power-domain-names = "a", "b";

> +			resets = <&cpg 112>;

Is this a reset line? Is it a clock? I see this pattern used throughout
the Renesas dts, but I'm just thinking how this will interact with the
powervr driver. The reset line is optional since some hardware
integrations manage it for us during the power-up/down sequences, which
appears to be the case here with the MSTP control (from my brief dig
through the Renesas TRM).

Related, see my comments on the bindings patch (P1/3) about how clocks
are wired up in this SoC.

Cheers,
Matt

> +		};
> +
>  		pciec0: pcie at fe000000 {
>  			compatible = "renesas,pcie-r8a7796",
>  				     "renesas,pcie-rcar-gen3";

-- 
Matt Coster
E: matt.coster at imgtec.com
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