[PATCH 27/39] dt-bindings: display: bridge: Document NXP i.MX95 pixel link support

[Frank Li]

On Sat, Oct 11, 2025 at 06:51:42PM +0200, Marek Vasut wrote:
> Document NXP i.MX95 pixel link bridge support.
>
> Signed-off-by: Marek Vasut <marek.vasut at mailbox.org>
> ---
> Cc: Abel Vesa <abelvesa at kernel.org>
> Cc: Conor Dooley <conor+dt at kernel.org>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: Krzysztof Kozlowski <krzk+dt at kernel.org>
> Cc: Laurent Pinchart <Laurent.pinchart at ideasonboard.com>
> Cc: Liu Ying <victor.liu at nxp.com>
> Cc: Lucas Stach <l.stach at pengutronix.de>
> Cc: Peng Fan <peng.fan at nxp.com>
> Cc: Pengutronix Kernel Team <kernel at pengutronix.de>
> Cc: Rob Herring <robh at kernel.org>
> Cc: Shawn Guo <shawnguo at kernel.org>
> Cc: Thomas Zimmermann <tzimmermann at suse.de>
> Cc: devicetree at vger.kernel.org
> Cc: dri-devel at lists.freedesktop.org
> Cc: imx at lists.linux.dev
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-clk at vger.kernel.org
> ---
>  .../display/bridge/fsl,imx95-pixel-link.yaml  | 101 ++++++++++++++++++
>  1 file changed, 101 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-link.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-link.yaml
> new file mode 100644
> index 0000000000000..b37888adfa45e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-link.yaml
> @@ -0,0 +1,101 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/fsl,imx95-pixel-link.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX95 Display Pixel Link
> +
> +maintainers:
> +  - Liu Ying <victor.liu at nxp.com>
> +  - Marek Vasut <marek.vasut at mailbox.org>
> +
> +description: |

use >

> +  The Freescale i.MX95 Display Pixel Link (DPL) forms a standard
> +  asynchronous linkage between pixel sources (display controller
> +  or camera module) and pixel consumers(imaging or displays).
> +  It consists of two distinct functions, a pixel transfer function
> +  and a control interface. Multiple pixel channels can exist per one
> +  control channel. This binding documentation is only for pixel links
> +  whose pixel sources are display controllers.
> +
> +  The i.MX95 Display Pixel Link is accessed via syscon.
> +
> +properties:
> +  compatible:
> +    const: fsl,imx95-dc-pixel-link
> +
> +  fsl,dc-stream-id:
> +    $ref: /schemas/types.yaml#/definitions/uint8
> +    description: |

Needn't |

why need this id

> +      u8 value representing the display controller stream index that the pixel
> +      link connects to.
> +    enum: [0, 1]
> +
> +  fsl,syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: |
> +      A phandle which points to Control and Status Registers (CSR) module.

Why not use stardard interface, like reset, clock, phy ...

> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    properties:
> +      port at 0:
> +        $ref: /schemas/graph.yaml#/properties/port

video-interfaces.yaml?

> +        description: The pixel link input port node from upstream video source.
> +
> +      port at 1:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: The pixel link output port node to downstream bridge.
> +
> +    required:
> +      - port at 0
> +      - port at 1
> +
> +required:
> +  - compatible
> +  - fsl,dc-stream-id
> +  - fsl,syscon
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    dc0-pixel-link0 {
> +        compatible = "fsl,imx95-dc-pixel-link";
> +        fsl,dc-stream-id = /bits/ 8 <0>;
> +        fsl,syscon = <&dispmix_csr>;
> +
> +        ports {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            /* from DC 0 pixel interleaver channel0 */
> +            port at 0 {
> +                reg = <0>;
> +
> +                dc0_pixel_link0_dc0_pixel_interleaver_ch0: endpoint {
> +                    remote-endpoint = <&dc0_pixel_interleaver_ch0_dc0_pixel_link0>;
> +                };
> +            };
> +
> +            /* to MIPI/LVDS combo subsystems */
> +            port at 1 {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +                reg = <1>;
> +
> +                dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint at 0 {

Needn't label dc0_pixel_link0_mipi_lvds_0_pxl2dpi

> +                    reg = <0>;
> +                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
> +                };
> +
> +                dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint at 1 {
> +                    reg = <1>;
> +                    remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
> +                };
> +            };
> +        };
> +    };
> --
> 2.51.0
>