[PATCH 25/39] dt-bindings: display: bridge: Document NXP i.MX95 pixel interleaver support

[Marek Vasut]

Document NXP i.MX95 pixel interleaver bridge support.

Signed-off-by: Marek Vasut <marek.vasut at mailbox.org>
---
Cc: Abel Vesa <abelvesa at kernel.org>
Cc: Conor Dooley <conor+dt at kernel.org>
Cc: Fabio Estevam <festevam at gmail.com>
Cc: Krzysztof Kozlowski <krzk+dt at kernel.org>
Cc: Laurent Pinchart <Laurent.pinchart at ideasonboard.com>
Cc: Liu Ying <victor.liu at nxp.com>
Cc: Lucas Stach <l.stach at pengutronix.de>
Cc: Peng Fan <peng.fan at nxp.com>
Cc: Pengutronix Kernel Team <kernel at pengutronix.de>
Cc: Rob Herring <robh at kernel.org>
Cc: Shawn Guo <shawnguo at kernel.org>
Cc: Thomas Zimmermann <tzimmermann at suse.de>
Cc: devicetree at vger.kernel.org
Cc: dri-devel at lists.freedesktop.org
Cc: imx at lists.linux.dev
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-clk at vger.kernel.org
---
 .../bridge/fsl,imx95-pixel-interleaver.yaml   | 85 +++++++++++++++++++
 1 file changed, 85 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-interleaver.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-interleaver.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-interleaver.yaml
new file mode 100644
index 0000000000000..6a0647f060a02
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-interleaver.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx95-pixel-interleaver.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX95 Display Pixel Interleaver
+
+maintainers:
+  - Liu Ying <victor.liu at nxp.com>
+  - Marek Vasut <marek.vasut at mailbox.org>
+
+description: |
+  The Freescale i.MX95 Display Pixel Interleaver receives and processes
+  2 input display streams from the display controller and routes those
+  to 3 pixel link output ports. The interleaver is capable of YUV444 to
+  YUV422 conversion and pixel interleaving.
+
+properties:
+  compatible:
+    const: fsl,imx95-pixel-interleaver
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  fsl,syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: |
+      A phandle which points to Control and Status Registers (CSR) module.
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port at 0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: The pixel link input port node from upstream video source.
+
+      port at 1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: The pixel link output port node to downstream bridge.
+
+    required:
+      - port at 0
+      - port at 1
+
+required:
+  - compatible
+  - fsl,syscon
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    bridge at 4b0d0000 {
+        compatible = "fsl,imx95-pixel-interleaver";
+        reg = <0x4b0d0000 0x50>;
+        clocks = <&scmi_clk 0>;
+        fsl,syscon = <&dispmix_csr>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port at 0 {
+                reg = <0>;
+
+                pixel_interleaver_disp0_to_dpu_disp0: endpoint {
+                    remote-endpoint = <&dpu_disp0_to_pixel_interleaver_disp0>;
+                };
+            };
+
+            port at 1 {
+                reg = <1>;
+
+                pixel_interleaver_disp0_to_display_pixel_link0: endpoint {
+                    remote-endpoint = <&display_pixel_link0_to_pixel_interleaver_disp0>;
+                };
+            };
+        };
+    };
-- 
2.51.0