[PATCH v3 5/5] coresight: docs: Document etm4x ts_interval

[Mike Leach]

On Thu, 2 Oct 2025 at 11:10, James Clark <james.clark at linaro.org> wrote:
>
> Document how the new field is used, maximum value and the interaction
> with SYNC timestamps.
>
> Signed-off-by: James Clark <james.clark at linaro.org>
> ---
>  Documentation/trace/coresight/coresight.rst | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst
> index 806699871b80..0cd83119b83f 100644
> --- a/Documentation/trace/coresight/coresight.rst
> +++ b/Documentation/trace/coresight/coresight.rst
> @@ -619,6 +619,20 @@ They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/
>       - Cycle count threshold value. If nothing is provided here or the provided value is 0, then the
>         default value i.e 0x100 will be used. If provided value is less than minimum cycles threshold
>         value, as indicated via TRCIDR3.CCITMIN, then the minimum value will be used instead.
> +   * - ts_level
> +     - Controls frequency of timestamps. The reload value of the
> +       timestamp counter is 2 raised to the power of this value. If the value is
> +       0 then the reload value is 1, if the value is 10 then the reload value is
> +       1024. Maximum allowed value is 15, and setting the maximum disables
> +       generation of timestamps via the counter, freeing the counter resources.
> +       Timestamps will be generated after 2 ^ ts_level cycles.
> +
> +       Separately to this value, timestamps will also be emitted when a SYNC
> +       packet is generated, although this is only for every 4096 bytes of trace.
> +       Therefore it's not possible to generate timestamps less frequently than
> +       that and ts_level timestamps are always in addition to SYNC timestamps.
> +       Timestamps must be enabled for this to have effect.
> +
>
>  How to use the STM module
>  -------------------------
>
> --
> 2.34.1
>

Reviewed-by: Mike Leach <mike.leach at linaro.org>

-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK