[PATCH AUTOSEL 6.17-6.12] arm64: zynqmp: Disable coresight by default

[Sasha Levin]

From: Quanyang Wang <quanyang.wang at windriver.com>

[ Upstream commit 0e3f9140ad04dca9a6a93dd6a6decdc53fd665ca ]

When secure-boot mode of bootloader is enabled, the registers of
coresight are not permitted to access that's why disable it by default.

Signed-off-by: Quanyang Wang <quanyang.wang at windriver.com>
Signed-off-by: Michal Simek <michal.simek at amd.com>
Link: https://lore.kernel.org/r/7e308b8efe977c4912079b4d1b1ab3d24908559e.1756799774.git.michal.simek@amd.com
Signed-off-by: Sasha Levin <sashal at kernel.org>
---

LLM Generated explanations, may be completely bogus:

YES – default‑disabling the ZynqMP CPU debug Coresight nodes is a
necessary regression fix for stable kernels that picked up the earlier
enablement.

- **Regression introduced**: Commit `fbce12d2899c4` (“arm64: zynqmp: Add
  coresight cpu debug support”) first added the `cpu[0-3]_debug` nodes
  without a `status` property, so they now probe by default; this change
  landed in v6.11 (`arch/arm64/boot/dts/xilinx/zynqmp.dtsi:548`, `:555`,
  `:562`, `:569`).
- **Failure mode**: On secure‑boot deployments the firmware prevents
  access to those debug registers, causing the `coresight-cpu-debug`
  driver to hit denied reads/writes during probe (see the unconditional
  register accesses in `drivers/hwtracing/coresight/coresight-cpu-
  debug.c:135` and :327). Because the driver auto-loads (module alias on
  the AMBA bus) with `CONFIG_CORESIGHT_CPU_DEBUG=m`
  (`arch/arm64/configs/defconfig`), this results in synchronous
  aborts/panics rather than a recoverable error.
- **What the patch does**: Adding `status = "disabled";` to each node
  (`arch/arm64/boot/dts/xilinx/zynqmp.dtsi:548`, `:555`, `:562`, `:569`)
  restores the pre‑v6.11 behavior: the coresight CPU debug blocks stay
  off unless a board DTS explicitly re-enables them. This mirrors how
  other SoCs handle similar hardware constraints (e.g.
  `arch/arm64/boot/dts/qcom/msm8916.dtsi` already defaults these nodes
  to `"disabled"`), and keeps the existing clock wiring in `zynqmp-clk-
  ccf.dtsi` harmless for boards that opt in.
- **Risk assessment**: The change is minimal, device-tree only, and
  reverts functionality that was never present before v6.11. Systems
  depending on the new default-on behavior can still override the status
  in board-specific DTS, while the patch prevents fatal boot failures on
  secure-booted systems. No additional dependencies are required for
  stable backports.

Given the severity of the regression and the contained nature of the
fix, this commit is a solid candidate for backporting to all stable
series that include `fbce12d2899c4`.

 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index e11d282462bd3..23d867c03263d 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -550,6 +550,7 @@ cpu0_debug: debug at fec10000 {
 			reg = <0x0 0xfec10000 0x0 0x1000>;
 			clock-names = "apb_pclk";
 			cpu = <&cpu0>;
+			status = "disabled";
 		};
 
 		cpu1_debug: debug at fed10000 {
@@ -557,6 +558,7 @@ cpu1_debug: debug at fed10000 {
 			reg = <0x0 0xfed10000 0x0 0x1000>;
 			clock-names = "apb_pclk";
 			cpu = <&cpu1>;
+			status = "disabled";
 		};
 
 		cpu2_debug: debug at fee10000 {
@@ -564,6 +566,7 @@ cpu2_debug: debug at fee10000 {
 			reg = <0x0 0xfee10000 0x0 0x1000>;
 			clock-names = "apb_pclk";
 			cpu = <&cpu2>;
+			status = "disabled";
 		};
 
 		cpu3_debug: debug at fef10000 {
@@ -571,6 +574,7 @@ cpu3_debug: debug at fef10000 {
 			reg = <0x0 0xfef10000 0x0 0x1000>;
 			clock-names = "apb_pclk";
 			cpu = <&cpu3>;
+			status = "disabled";
 		};
 
 		/* GDMA */
-- 
2.51.0