[PATCH v11 05/17] media: dt-bindings: add rockchip rk3568 mipi csi-2 receiver
Michael Riesch
michael.riesch at collabora.com
Thu Oct 9 02:09:52 PDT 2025
Hi Sakari,
On 10/7/25 22:00, Sakari Ailus wrote:
> Hi Michael,
>
> On Wed, Sep 17, 2025 at 05:38:45PM +0200, Michael Riesch via B4 Relay wrote:
>> From: Michael Riesch <michael.riesch at collabora.com>
>>
>> Add documentation for the Rockchip RK3568 MIPI CSI-2 Receiver.
>>
>> Signed-off-by: Michael Riesch <michael.riesch at wolfvision.net>
>> Reviewed-by: Bryan O'Donoghue <bod at kernel.org>
>> Signed-off-by: Michael Riesch <michael.riesch at collabora.com>
>> ---
>> .../bindings/media/rockchip,rk3568-mipi-csi.yaml | 144 +++++++++++++++++++++
>> MAINTAINERS | 6 +
>> 2 files changed, 150 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi.yaml
>> new file mode 100644
>> index 000000000000..8cbab93b4b85
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi.yaml
>> @@ -0,0 +1,144 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/media/rockchip,rk3568-mipi-csi.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Rockchip RK3568 MIPI CSI-2 Receiver
>> +
>> +maintainers:
>> + - Michael Riesch <michael.riesch at collabora.com>
>> +
>> +description:
>> + The Rockchip RK3568 MIPI CSI-2 Receiver is a CSI-2 bridge with one input port
>> + and one output port. It receives the data with the help of an external
>> + MIPI PHY (C-PHY or D-PHY) and passes it to the Rockchip RK3568 Video Capture
>> + (VICAP) block.
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - items:
>> + - enum:
>> + - rockchip,rk3588-mipi-csi
>> + - const: rockchip,rk3568-mipi-csi
>> + - const: rockchip,rk3568-mipi-csi
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + interrupts:
>> + items:
>> + - description: Interrupt that signals changes in CSI2HOST_ERR1.
>> + - description: Interrupt that signals changes in CSI2HOST_ERR2.
>> +
>> + interrupt-names:
>> + items:
>> + - const: irq1
>> + - const: irq2
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + phys:
>> + maxItems: 1
>> + description: MIPI C-PHY or D-PHY.
>> +
>> + ports:
>> + $ref: /schemas/graph.yaml#/properties/ports
>> +
>> + properties:
>> + port at 0:
>> + $ref: /schemas/graph.yaml#/$defs/port-base
>> + unevaluatedProperties: false
>> + description: Input port node. Connect to e.g., a MIPI CSI-2 image sensor.
>> +
>> + properties:
>> + endpoint:
>> + $ref: video-interfaces.yaml#
>> + unevaluatedProperties: false
>> +
>> + properties:
>> + bus-type:
>> + enum: [1, 4]
>> +
>> + data-lanes:
>> + minItems: 1
>> + maxItems: 4
>> +
>> + required:
>> + - bus-type
>> + - data-lanes
>> +
>> + port at 1:
>> + $ref: /schemas/graph.yaml#/properties/port
>> + description: Output port connected to a RK3568 VICAP port.
>
> As the VICAP port appears to be a DVP/Bt.565 receiver, also this output can
> presumably be connected elsewhere, too.
Not quite. One VICAP port is the DVP (and can receive BT.656, amongst
others), but there may be one or more ports that are connected to the
MIPI CSI-2 receiver(s). See the VICAP binding.
> Either way, aren't signal polarity or sampling related properties relevant
> here, too, and perhaps more so for the VICAP bindings?
No, I don't think so. This is some internal HW connection. No idea how
Rockchip glued the MIPI CSI-2 receiver(s) to the corresponding VICAP
port(s), and there is nothing one could tweak or adjust or configure...
Best regards,
Michael
> See e.g.
> Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml .
>
>> +
>> + required:
>> + - port at 0
>> + - port at 1
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + resets:
>> + maxItems: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - phys
>> + - ports
>> + - power-domains
>> + - resets
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/rk3568-cru.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/media/video-interfaces.h>
>> + #include <dt-bindings/power/rk3568-power.h>
>> +
>> + soc {
>> + interrupt-parent = <&gic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + csi: csi at fdfb0000 {
>> + compatible = "rockchip,rk3568-mipi-csi";
>> + reg = <0x0 0xfdfb0000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "irq1", "irq2";
>> + clocks = <&cru PCLK_CSI2HOST1>;
>> + phys = <&csi_dphy>;
>> + power-domains = <&power RK3568_PD_VI>;
>> + resets = <&cru SRST_P_CSI2HOST1>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + csi_in: port at 0 {
>> + reg = <0>;
>> +
>> + csi_input: endpoint {
>> + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
>> + data-lanes = <1 2 3 4>;
>> + remote-endpoint = <&imx415_output>;
>> + };
>> + };
>> +
>> + csi_out: port at 1 {
>> + reg = <1>;
>> +
>> + csi_output: endpoint {
>> + remote-endpoint = <&vicap_mipi_input>;
>> + };
>> + };
>> + };
>> + };
>> + };
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 4c39b9fd80bb..2ac4b7a5b255 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -21797,6 +21797,12 @@ F: Documentation/userspace-api/media/v4l/metafmt-rkisp1.rst
>> F: drivers/media/platform/rockchip/rkisp1
>> F: include/uapi/linux/rkisp1-config.h
>>
>> +ROCKCHIP MIPI CSI-2 RECEIVER DRIVER
>> +M: Michael Riesch <michael.riesch at collabora.com>
>> +L: linux-media at vger.kernel.org
>> +S: Maintained
>> +F: Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi.yaml
>> +
>> ROCKCHIP RK3568 RANDOM NUMBER GENERATOR SUPPORT
>> M: Daniel Golle <daniel at makrotopia.org>
>> M: Aurelien Jarno <aurelien at aurel32.net>
>>
>
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