[PATCH v2 2/5] mmc: sdhci-brcmstb: move SDIO_CFG_CQ_CAPABILITY define

[Adrian Hunter]

On 07/10/2025 17:04, Kamal Dasu wrote:
> Moving SDIO_CFG_CQ_CAPABILITY register defines to be in sorted order for
> better readability.
> 
> Signed-off-by: Kamal Dasu <kamal.dasu at broadcom.com>

Acked-by: Adrian Hunter <adrian.hunter at intel.com>

> ---
>  drivers/mmc/host/sdhci-brcmstb.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c
> index efc2f3bdc631..f81cc1889ac9 100644
> --- a/drivers/mmc/host/sdhci-brcmstb.c
> +++ b/drivers/mmc/host/sdhci-brcmstb.c
> @@ -31,13 +31,11 @@
>  
>  #define SDHCI_ARASAN_CQE_BASE_ADDR		0x200
>  
> -#define SDIO_CFG_CQ_CAPABILITY			0x4c
> -#define SDIO_CFG_CQ_CAPABILITY_FMUL		GENMASK(13, 12)
> -
>  #define SDIO_CFG_CTRL				0x0
>  #define SDIO_CFG_CTRL_SDCD_N_TEST_EN		BIT(31)
>  #define SDIO_CFG_CTRL_SDCD_N_TEST_LEV		BIT(30)
> -
> +#define SDIO_CFG_CQ_CAPABILITY			0x4c
> +#define SDIO_CFG_CQ_CAPABILITY_FMUL		GENMASK(13, 12)
>  #define SDIO_CFG_MAX_50MHZ_MODE			0x1ac
>  #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE	BIT(31)
>  #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE		BIT(0)