[PATCH v2 1/4] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3
Krzysztof Kozlowski
krzk at kernel.org
Wed Oct 8 16:56:26 PDT 2025
On 08/10/2025 14:59, Roy Luo wrote:
> Document the device tree bindings for the DWC3 USB controller found in
> Google Tensor SoCs, starting with the G5 generation.
>
> The Tensor G5 silicon represents a complete architectural departure from
G5 does not have a model number like G1-G4?
> previous generations (like gs101), including entirely new clock/reset
> schemes, top-level wrapper and register interface. Consequently,
> existing Samsung/Exynos DWC3 USB bindings and drivers are incompatible,
Do not reference drivers. Explain the hardware.
> necessitating this new device tree binding.
>
> The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features
> Dual-Role Device single port with hibernation support.
>
> Signed-off-by: Roy Luo <royluo at google.com>
> ---
> .../bindings/usb/google,gs-dwc3.yaml | 145 ++++++++++++++++++
> 1 file changed, 145 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml
> new file mode 100644
> index 000000000000..9eb0bf726e8d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml
> @@ -0,0 +1,145 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (c) 2025, Google LLC
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/google,gs-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Google Tensor Series (G5+) DWC3 USB SoC Controller
> +
> +maintainers:
> + - Roy Luo <royluo at google.com>
> +
> +description: |
Do not need '|' unless you need to preserve formatting.
> + Describes the DWC3 USB controller block implemented on Google Tensor SoCs,
> + starting with the G5 generation. Based on Synopsys DWC3 IP, the controller
> + features Dual-Role Device single port with hibernation add-on.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - google,gs5-dwc3
> +
> + reg:
> + minItems: 3
Drop
> + maxItems: 3
> +
> + reg-names:
> + description: |
> + The following memory regions must present:
> + - dwc3_core: Core DWC3 IP registers.
> + - host_cfg_csr: Hibernation control registers.
> + - usbint_csr: Hibernation interrupt registers.
Drop description or move it to items in reg. See other bindings.
> + items:
> + - const: dwc3_core
> + - const: host_cfg_csr
> + - const: usbint_csr
> +
> + interrupts:
> + minItems: 3
Drop
> + maxItems: 3
> +
> + interrupt-names:
> + description: |
> + The following interrupts must present:
> + - dwc_usb3: Core DWC3 interrupt.
> + - hs_pme_irq: High speed remote wakeup interrupt for hibernation.
> + - ss_pme_irq: Super speed remote wakeup interrupt for hibernation.
>From where did you get this style? Don't write bindings with chat gpt or
whatever other tool. it is a waste of our time.
> + items:
> + - const: dwc_usb3
> + - const: hs_pme_irq
> + - const: ss_pme_irq
> +
> + clocks:
> + minItems: 3
> + maxItems: 3
> +
> + clock-names:
> + minItems: 3
> + maxItems: 3
>From where did you get such syntax?
> +
> + resets:
> + minItems: 5
> + maxItems: 5
> +
> + reset-names:
> + items:
> + - const: usbc_non_sticky
> + - const: usbc_sticky
> + - const: usb_drd_bus
> + - const: u2phy_apb
> + - const: usb_top_csr
> +
> + power-domains:
> + minItems: 2
> + maxItems: 2
> +
> + power-domain-names:
> + description: |
> + The following power domain must present:
> + - usb_psw_pd: The child power domain of usb_top_pd. Turning it on puts the controller
> + into full power state, turning it off puts the controller into power
> + gated state.
> + - usb_top_pd: The parent power domain of usb_psw_pd. Turning it on puts the controller
> + into power gated state, turning it off completely shuts off the
> + controller.
Same comments.
> + items:
> + - const: usb_psw_pd
> + - const: usb_top_pd
> +
> + iommus:
> + maxItems: 1
> +
Best regards,
Krzysztof
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