[PATCH v1 2/2] arm64: dts: xilinx: add soc-specific spi compatibles for zynqmp/versal-net

[Michal Simek]

On 10/1/25 20:31, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
> 
> Unlike zynq, which has a specific compatible for the Cadence spi
> controller, zynqmp and versal-net do not have specific compatibles.
> In order to "encourage" people to use soc-specific compatibles for new
> devices using this IP, add specific compatibles for these devices, with
> a fallback to the existing compatible for the r1p6 version of the IP so
> that there will be no functional change.
> 
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
> CC: Jun Guo <Jun.Guo at cixtech.com>
> CC: Mark Brown <broonie at kernel.org>
> CC: Rob Herring <robh at kernel.org>
> CC: Krzysztof Kozlowski <krzk+dt at kernel.org>
> CC: Conor Dooley <conor+dt at kernel.org>
> CC: Michal Simek <michal.simek at amd.com>
> CC: linux-spi at vger.kernel.org
> CC: devicetree at vger.kernel.org
> CC: linux-kernel at vger.kernel.org
> CC: linux-arm-kernel at lists.infradead.org
> ---
>   arch/arm64/boot/dts/xilinx/versal-net.dtsi | 4 ++--
>   arch/arm64/boot/dts/xilinx/zynqmp.dtsi     | 4 ++--
>   2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi
> index fc9f49e57385..38af1a4e34f7 100644
> --- a/arch/arm64/boot/dts/xilinx/versal-net.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi
> @@ -610,7 +610,7 @@ smmu: iommu at ec000000 {
>   		};
>   
>   		spi0: spi at f1960000 {
> -			compatible = "cdns,spi-r1p6";
> +			compatible = "xlnx,versal-net-spi-r1p6", "cdns,spi-r1p6";
>   			status = "disabled";
>   			interrupts = <0 23 4>;
>   			reg = <0 0xf1960000 0 0x1000>;
> @@ -618,7 +618,7 @@ spi0: spi at f1960000 {
>   		};
>   
>   		spi1: spi at f1970000 {
> -			compatible = "cdns,spi-r1p6";
> +			compatible = "xlnx,versal-net-spi-r1p6", "cdns,spi-r1p6";
>   			status = "disabled";
>   			interrupts = <0 24 4>;
>   			reg = <0 0xf1970000 0 0x1000>;
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index e11d282462bd..89c565bef274 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -1076,7 +1076,7 @@ smmu: iommu at fd800000 {
>   		};
>   
>   		spi0: spi at ff040000 {
> -			compatible = "cdns,spi-r1p6";
> +			compatible = "xlnx,zynqmp-spi-r1p6", "cdns,spi-r1p6";
>   			status = "disabled";
>   			interrupt-parent = <&gic>;
>   			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1088,7 +1088,7 @@ spi0: spi at ff040000 {
>   		};
>   
>   		spi1: spi at ff050000 {
> -			compatible = "cdns,spi-r1p6";
> +			compatible = "xlnx,zynqmp-spi-r1p6", "cdns,spi-r1p6";
>   			status = "disabled";
>   			interrupt-parent = <&gic>;
>   			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

Acked-by: Michal Simek <michal.simek at amd.com>

Do you expect to go via SPI tree or via SOC tree?

Thanks,
Michal