[PATCH v1 1/2] spi: dt-bindings: cadence: add soc-specific compatible strings for zynqmp and versal-net
Michal Simek
michal.simek at amd.com
Wed Oct 1 23:05:32 PDT 2025
On 10/1/25 20:31, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
>
> When the binding for the Cadence spi controller was written, a dedicated
> compatible was added for the zynq device. Later when zynqmp and
> versal-net, which also use this spi controller IP, were added they did
> not receive soc-specific compatibles. Add them now, with a fallback to
> the existing compatible for the r1p6 version of the IP so that there
> will be no functional change. Retain the r1p6 in the string, to match
> what was done for zynq.
>
> Disallow the cdns,spi-r1p6 compatible in isolation to "encourage" people
> to actually add soc-specific compatible strings in the future.
>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
> CC: Jun Guo <Jun.Guo at cixtech.com>
> CC: Mark Brown <broonie at kernel.org>
> CC: Rob Herring <robh at kernel.org>
> CC: Krzysztof Kozlowski <krzk+dt at kernel.org>
> CC: Conor Dooley <conor+dt at kernel.org>
> CC: Michal Simek <michal.simek at amd.com>
> CC: linux-spi at vger.kernel.org
> CC: devicetree at vger.kernel.org
> CC: linux-kernel at vger.kernel.org
> CC: linux-arm-kernel at lists.infradead.org
> ---
> .../devicetree/bindings/spi/spi-cadence.yaml | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
> index 8de96abe9da1..27414b78d61d 100644
> --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml
> +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
> @@ -14,9 +14,14 @@ allOf:
>
> properties:
> compatible:
> - enum:
> - - cdns,spi-r1p6
> - - xlnx,zynq-spi-r1p6
> + oneOf:
> + - enum:
> + - xlnx,zynq-spi-r1p6
> + - items:
> + - enum:
> + - xlnx,zynqmp-spi-r1p6
> + - xlnx,versal-net-spi-r1p6
> + - const: cdns,spi-r1p6
>
> reg:
> maxItems: 1
Acked-by: Michal Simek <michal.simek at amd.com>
Thanks,
Michal
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