[RFC v1 1/5] PCI: rockchip: Fix Link Control register offset and enable ASPM/CLKREQ

[Bjorn Helgaas]

On Mon, Nov 17, 2025 at 11:40:09PM +0530, Anand Moon wrote:
> As per the RK3399 TRM (Part 2, 17.6.6.1.31), the Link Control register
> (RC_CONFIG_LC) resides at an offset of 0xd0 within the Root Complex (RC)
> configuration space, not at the offset of the PCI Express Capability List
> (0xc0). Following changes correct the register offset to use
> PCIE_RC_CONFIG_LC (0xd0) to configure link control.
> 
> Additionally, this commit explicitly enables ASPM (Active State Power
> Management) control and the CLKREQ# (Clock Request) mechanism as part of
> the Link Control register programming when enabling bandwidth
> notifications.

Don't do two things at once in the same patch.  Fix the register
offset in one patch.  Actually, as I mentioned at [1], there's a lot
of fixing to do there, and I'm not even going to consider other
changes until the #define mess is cleaned up.

What I'd really like to see is at least two patches here: one that
clearly makes no functional change -- don't try to fix anything, just
make it 100% obvious that all the offsets stay the same.  Then make a
separate patch that *only* changes any of the offsets that are wrong.

I don't think there should even be an ASPM change.  The PCI core
should be enabling L0s and L1 itself for DT systems like this.  And
ASPM needs to be enabled only when both ends of the link support it,
and only in a specific order.  The PCI core pays attention to that,
but this patch does not.

Bjorn

[1] https://lore.kernel.org/r/20251118005056.GA2541796@bhelgaas