[PATCH v4 01/13] coresight: Change syncfreq to be a u8

[Leo Yan]

On Wed, Nov 12, 2025 at 03:22:07PM +0000, James Clark wrote:
> TRCSYNCPR.PERIOD is the only functional part of TRCSYNCPR and it only
> has 5 valid bits so it can be stored in a u8.
> 
> Reviewed-by: Mike Leach <mike.leach at linaro.org>
> Signed-off-by: James Clark <james.clark at linaro.org>

Reviewed-by: Leo Yan <leo.yan at arm.com>

> ---
>  drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 8d4a1f0f1e52..56a359184c6f 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -826,7 +826,6 @@ struct etmv4_config {
>  	u32				eventctrl1;
>  	u32				stall_ctrl;
>  	u32				ts_ctrl;
> -	u32				syncfreq;
>  	u32				ccctlr;
>  	u32				bb_ctrl;
>  	u32				vinst_ctrl;
> @@ -834,6 +833,7 @@ struct etmv4_config {
>  	u32				vissctlr;
>  	u32				vipcssctlr;
>  	u8				seq_idx;
> +	u8				syncfreq;
>  	u32				seq_ctrl[ETM_MAX_SEQ_STATES];
>  	u32				seq_rst;
>  	u32				seq_state;
> 
> -- 
> 2.34.1
>