[PATCH 15/33] arm_mpam: Add helpers for managing the locking around the mon_sel registers

[Shaopeng Tan (Fujitsu)]

> From: James Morse <james.morse at arm.com>
> 
> The MSC MON_SEL register needs to be accessed from hardirq for the overflow
> interrupt, and when taking an IPI to access these registers on platforms where
> MSC are not accessible from every CPU. This makes an irqsave spinlock the
> obvious lock to protect these registers. On systems with SCMI or PCC
> mailboxes it must be able to sleep, meaning a mutex must be used.
> The SCMI or PCC platforms can't support an overflow interrupt, and can't
> access the registers from hardirq context.
> 
> Clearly these two can't exist for one MSC at the same time.
> 
> Add helpers for the MON_SEL locking. For now, use a irqsave spinlock and only
> support 'real' MMIO platforms.
> 
> In the future this lock will be split in two allowing SCMI/PCC platforms to take
> a mutex. Because there are contexts where the SCMI/PCC platforms can't
> make an access, mpam_mon_sel_lock() needs to be able to fail. Do this now,
> so that all the error handling on these paths is present. This allows the relevant
> paths to fail if they are needed on a platform where this isn't possible, instead
> of having to make explicit checks of the interface type.
> 
> Tested-by: Fenghua Yu <fenghuay at nvidia.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron at huawei.com>
> Tested-by: Shaopeng Tan <tan.shaopeng at jp.fujitsu.com>
> Tested-by: Peter Newman <peternewman at google.com>
> Signed-off-by: James Morse <james.morse at arm.com>
> Signed-off-by: Ben Horgan <ben.horgan at arm.com>
> ---

Reviewed-by: Shaopeng Tan <tan.shaopeng at jp.fujitsu.com>