[PATCH 1/4 v4] dt-bindings: PCI: s32g: Add NXP PCIe controller

[Frank Li]

On Mon, Nov 10, 2025 at 06:33:31PM +0100, Vincent Guittot wrote:
> Describe the PCIe host controller available on the S32G platforms.
>
> Co-developed-by: Ionut Vicovan <Ionut.Vicovan at nxp.com>
> Signed-off-by: Ionut Vicovan <Ionut.Vicovan at nxp.com>
> Co-developed-by: Bogdan-Gabriel Roman <bogdan-gabriel.roman at nxp.com>
> Signed-off-by: Bogdan-Gabriel Roman <bogdan-gabriel.roman at nxp.com>
> Co-developed-by: Larisa Grigore <larisa.grigore at nxp.com>
> Signed-off-by: Larisa Grigore <larisa.grigore at nxp.com>
> Co-developed-by: Ghennadi Procopciuc <Ghennadi.Procopciuc at nxp.com>
> Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc at nxp.com>
> Co-developed-by: Ciprian Marian Costea <ciprianmarian.costea at nxp.com>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea at nxp.com>
> Co-developed-by: Bogdan Hamciuc <bogdan.hamciuc at nxp.com>
> Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc at nxp.com>
> Signed-off-by: Vincent Guittot <vincent.guittot at linaro.org>
> ---
>  .../bindings/pci/nxp,s32g-pcie.yaml           | 130 ++++++++++++++++++
>  1 file changed, 130 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
> new file mode 100644
> index 000000000000..6077c251c2cd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
> @@ -0,0 +1,130 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/nxp,s32g-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP S32G2xxx/S32G3xxx PCIe Root Complex controller
> +
> +maintainers:
> +  - Bogdan Hamciuc <bogdan.hamciuc at nxp.com>
> +  - Ionut Vicovan <ionut.vicovan at nxp.com>
> +
> +description:
> +  This PCIe controller is based on the Synopsys DesignWare PCIe IP.
> +  The S32G SoC family has two PCIe controllers, which can be configured as
> +  either Root Complex or Endpoint.
> +
> +allOf:
> +  - $ref: /schemas/pci/snps,dw-pcie.yaml#

Suggest move allOf after required, in case add if-else branch later.

> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - enum:
> +          - nxp,s32g2-pcie
> +      - items:
> +          - const: nxp,s32g3-pcie
> +          - const: nxp,s32g2-pcie
> +
> +  reg:
> +    maxItems: 6
> +
> +  reg-names:
> +    items:
> +      - const: dbi
> +      - const: dbi2
> +      - const: atu
> +      - const: dma
> +      - const: ctrl
> +      - const: config
> +
> +  interrupts:
> +    maxItems: 2

Need match interrupt-names's restriction

      minItems: 1
      maxItems: 2

> +
> +  interrupt-names:
> +    items:
> +      - const: msi
> +      - const: dma
> +    minItems: 1
> +
...
> +
> +        pcie at 40400000 {
> +            compatible = "nxp,s32g3-pcie",
> +                         "nxp,s32g2-pcie";

put to one line to save LOC.

Frank
> +            reg = <0x00 0x40400000 0x0 0x00001000>,   /* dbi registers */
> +                  <0x00 0x40420000 0x0 0x00001000>,   /* dbi2 registers */
> +                  <0x00 0x40460000 0x0 0x00001000>,   /* atu registers */
> +                  <0x00 0x40470000 0x0 0x00001000>,   /* dma registers */
> +                  <0x00 0x40481000 0x0 0x000000f8>,   /* ctrl registers */
> +                  <0x5f 0xffffe000 0x0 0x00002000>;   /* config space */
...
> +            };
> +        };
> +    };
> --
> 2.43.0
>