[PATCH v1 2/3] arm64: dts: ti: Add Aquila AM69 Support

[Francesco Dolcini]

Hello Andrew,

On Thu, Nov 06, 2025 at 07:32:44AM -0600, Andrew Davis wrote:
> On 11/6/25 4:19 AM, Francesco Dolcini wrote:
> > On Wed, Nov 05, 2025 at 02:01:35PM -0600, Andrew Davis wrote:
> > > On 11/5/25 5:53 AM, Francesco Dolcini wrote:
> > > > On Tue, Nov 04, 2025 at 11:41:54AM -0600, Andrew Davis wrote:
> > > > > On 11/4/25 8:52 AM, Francesco Dolcini wrote:

...

> > > > > > +/* Aquila SPI_1 */
> > > > > > +&main_spi2 {
> > > > > > +	pinctrl-names = "default";
> > > > > > +	pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>;
> > > > > > +	status = "disabled";
> > > > > 
> > > > > This is already disabled by default in the SoC dtsi file.
> > > > 
> > > > Yes, known. Is this an issue?
> > > > 
> > > > This node must be disabled, no matter what is present in any included
> > > > dtsi file, it's a deliberate decision.
> > > > 
> > > > This dtsi file describes a SoM, the used pins/functions are defined on
> > > > the pinout, but this node cannot be enabled unless the SoM is mated with
> > > > a carrier board that is exposing it.
> > > 
> > > Same as my point above, you shouldn't enable nodes that are not used
> > > or have anything attached. The SoM only has some edge connectors so
> > > it should not be enabled at the SoM level, that we seem to agree, but
> > > the carrier board doesn't connect those lines to anything either. They
> > > just run to a pin header with nothing attached, how is that header
> > > any different than the pins on the edge of the SoM?
> > 
> > You are commenting something unrelated here, or I am not understanding
> > you.
> 
> Yes this was a bit of a tangent to the comment above. The point here
> was more on the pinmux, as a new carrier board might use these pins
> for something other than SPI, the pinmuxing shouldn't be done at the
> SoM dtsi level. Instead do it at the point the node is connected to
> some hardware on the carrier board in its DTS.

Our SoM implements a specific pinout, with well defined functions,
therefore the functionality of the pin is defined at the SoM level [1].

[1] https://docs1.toradex.com/116801-aquila_family_specification.pdf
	  page 13, 14, 15


Francesco