On 06/11/2025 09:57, Russell King (Oracle) wrote:
> Move the preparation of the PHY_INTF_SEL_x bitfield out of the switch()
> statement such that it only appears once.
>
> Signed-off-by: Russell King (Oracle) <rmk+kernel at armlinux.org.uk>
Reviewed-by: Maxime Chevallier <maxime.chevallier at bootlin.com>
Maxime
> ---
> .../ethernet/stmicro/stmmac/dwmac-ingenic.c | 34 +++++++++++++------
> 1 file changed, 23 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c
> index b56d7ada1939..6680f7d3a469 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ingenic.c
> @@ -71,20 +71,21 @@ static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
> {
> struct ingenic_mac *mac = plat_dat->bsp_priv;
> unsigned int val;
> + u8 phy_intf_sel;
>
> switch (plat_dat->phy_interface) {
> case PHY_INTERFACE_MODE_MII:
> - val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, PHY_INTF_SEL_GMII_MII);
> + phy_intf_sel = PHY_INTF_SEL_GMII_MII;
> dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n");
> break;
>
> case PHY_INTERFACE_MODE_GMII:
> - val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, PHY_INTF_SEL_GMII_MII);
> + phy_intf_sel = PHY_INTF_SEL_GMII_MII;
> dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_GMII\n");
> break;
>
> case PHY_INTERFACE_MODE_RMII:
> - val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, PHY_INTF_SEL_RMII);
> + phy_intf_sel = PHY_INTF_SEL_RMII;
> dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
> break;
>
> @@ -92,7 +93,7 @@ static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
> case PHY_INTERFACE_MODE_RGMII_ID:
> case PHY_INTERFACE_MODE_RGMII_TXID:
> case PHY_INTERFACE_MODE_RGMII_RXID:
> - val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, PHY_INTF_SEL_RGMII);
> + phy_intf_sel = PHY_INTF_SEL_RGMII;
> dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RGMII\n");
> break;
>
> @@ -102,7 +103,8 @@ static int jz4775_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
> return -EINVAL;
> }
>
> - val |= FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT);
> + val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel) |
> + FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT);
>
> /* Update MAC PHY control register */
> return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
> @@ -131,10 +133,11 @@ static int x1600_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
> {
> struct ingenic_mac *mac = plat_dat->bsp_priv;
> unsigned int val;
> + u8 phy_intf_sel;
>
> switch (plat_dat->phy_interface) {
> case PHY_INTERFACE_MODE_RMII:
> - val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, PHY_INTF_SEL_RMII);
> + phy_intf_sel = PHY_INTF_SEL_RMII;
> dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
> break;
>
> @@ -144,6 +147,8 @@ static int x1600_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
> return -EINVAL;
> }
>
> + val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
> +
> /* Update MAC PHY control register */
> return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
> }
> @@ -152,11 +157,12 @@ static int x1830_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
> {
> struct ingenic_mac *mac = plat_dat->bsp_priv;
> unsigned int val;
> + u8 phy_intf_sel;
>
> switch (plat_dat->phy_interface) {
> case PHY_INTERFACE_MODE_RMII:
> - val = FIELD_PREP(MACPHYC_MODE_SEL_MASK, MACPHYC_MODE_SEL_RMII) |
> - FIELD_PREP(MACPHYC_PHY_INFT_MASK, PHY_INTF_SEL_RMII);
> + val = FIELD_PREP(MACPHYC_MODE_SEL_MASK, MACPHYC_MODE_SEL_RMII);
> + phy_intf_sel = PHY_INTF_SEL_RMII;
> dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
> break;
>
> @@ -166,6 +172,8 @@ static int x1830_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
> return -EINVAL;
> }
>
> + val |= FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
> +
> /* Update MAC PHY control register */
> return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
> }
> @@ -174,12 +182,13 @@ static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
> {
> struct ingenic_mac *mac = plat_dat->bsp_priv;
> unsigned int val;
> + u8 phy_intf_sel;
>
> switch (plat_dat->phy_interface) {
> case PHY_INTERFACE_MODE_RMII:
> val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) |
> - FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN) |
> - FIELD_PREP(MACPHYC_PHY_INFT_MASK, PHY_INTF_SEL_RMII);
> + FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN);
> + phy_intf_sel = PHY_INTF_SEL_RMII;
> dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_RMII\n");
> break;
>
> @@ -187,7 +196,8 @@ static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
> case PHY_INTERFACE_MODE_RGMII_ID:
> case PHY_INTERFACE_MODE_RGMII_TXID:
> case PHY_INTERFACE_MODE_RGMII_RXID:
> - val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, PHY_INTF_SEL_RGMII);
> + val = 0;
> + phy_intf_sel = PHY_INTF_SEL_RGMII;
>
> if (mac->tx_delay == 0)
> val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN);
> @@ -210,6 +220,8 @@ static int x2000_mac_set_mode(struct plat_stmmacenet_data *plat_dat)
> return -EINVAL;
> }
>
> + val |= FIELD_PREP(MACPHYC_PHY_INFT_MASK, phy_intf_sel);
> +
> /* Update MAC PHY control register */
> return regmap_update_bits(mac->regmap, 0, mac->soc_info->mask, val);
> }