[PATCH v2 1/1] perf vendor events arm64 AmpereOneX: Fix spelling typo in the metrics file

[Arnaldo Carvalho de Melo]

On Mon, Nov 03, 2025 at 09:46:33AM +0800, Chu Guangqing wrote:
> The json file incorrectly used "acceses" instead of "accesses".

Acked-by: Arnaldo Carvalho de Melo <acme at redhat.com>
 
> Signed-off-by: Chu Guangqing <chuguangqing at inspur.com>
> ---
>  .../arch/arm64/ampere/ampereonex/metrics.json    | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json
> index 6817cac149e0..a29aadc9b2e3 100644
> --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json
> +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json
> @@ -388,55 +388,55 @@
>          "MetricExpr": "L1D_CACHE_RW / L1D_CACHE",
>          "BriefDescription": "L1D cache access - demand",
>          "MetricGroup": "Cache",
> -        "ScaleUnit": "100percent of cache acceses"
> +        "ScaleUnit": "100percent of cache accesses"
>      },
>      {
>          "MetricName": "l1d_cache_access_prefetches",
>          "MetricExpr": "L1D_CACHE_PRFM / L1D_CACHE",
>          "BriefDescription": "L1D cache access - prefetch",
>          "MetricGroup": "Cache",
> -        "ScaleUnit": "100percent of cache acceses"
> +        "ScaleUnit": "100percent of cache accesses"
>      },
>      {
>          "MetricName": "l1d_cache_demand_misses",
>          "MetricExpr": "L1D_CACHE_REFILL_RW / L1D_CACHE",
>          "BriefDescription": "L1D cache demand misses",
>          "MetricGroup": "Cache",
> -        "ScaleUnit": "100percent of cache acceses"
> +        "ScaleUnit": "100percent of cache accesses"
>      },
>      {
>          "MetricName": "l1d_cache_demand_misses_read",
>          "MetricExpr": "L1D_CACHE_REFILL_RD / L1D_CACHE",
>          "BriefDescription": "L1D cache demand misses - read",
>          "MetricGroup": "Cache",
> -        "ScaleUnit": "100percent of cache acceses"
> +        "ScaleUnit": "100percent of cache accesses"
>      },
>      {
>          "MetricName": "l1d_cache_demand_misses_write",
>          "MetricExpr": "L1D_CACHE_REFILL_WR / L1D_CACHE",
>          "BriefDescription": "L1D cache demand misses - write",
>          "MetricGroup": "Cache",
> -        "ScaleUnit": "100percent of cache acceses"
> +        "ScaleUnit": "100percent of cache accesses"
>      },
>      {
>          "MetricName": "l1d_cache_prefetch_misses",
>          "MetricExpr": "L1D_CACHE_REFILL_PRFM / L1D_CACHE",
>          "BriefDescription": "L1D cache prefetch misses",
>          "MetricGroup": "Cache",
> -        "ScaleUnit": "100percent of cache acceses"
> +        "ScaleUnit": "100percent of cache accesses"
>      },
>      {
>          "MetricName": "ase_scalar_mix",
>          "MetricExpr": "ASE_SCALAR_SPEC / OP_SPEC",
>          "BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) scalar operations",
>          "MetricGroup": "Instructions",
> -        "ScaleUnit": "100percent of cache acceses"
> +        "ScaleUnit": "100percent of cache accesses"
>      },
>      {
>          "MetricName": "ase_vector_mix",
>          "MetricExpr": "ASE_VECTOR_SPEC / OP_SPEC",
>          "BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) vector operations",
>          "MetricGroup": "Instructions",
> -        "ScaleUnit": "100percent of cache acceses"
> +        "ScaleUnit": "100percent of cache accesses"
>      }
>  ]
> -- 
> 2.43.7
>