[PATCH 24/30] drm/sun4i: mixer: Convert heuristics to quirk

[Chen-Yu Tsai]

On Mon, Oct 13, 2025 at 3:24 AM Jernej Skrabec <jernej.skrabec at gmail.com> wrote:
>
> Determination if FCC unit can be used for VI layer alpha depends on
> number of VI channels. This info won't be available anymore in future
> to VI layer driver because of DE33 way of allocating planes from same
> pool to different mixers.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec at gmail.com>
> ---
>  drivers/gpu/drm/sun4i/sun8i_mixer.c    |  9 +++++++++
>  drivers/gpu/drm/sun4i/sun8i_mixer.h    |  3 +++
>  drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 12 +++++++-----
>  3 files changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> index 267a6f75feb2..78bbfbe62833 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> @@ -707,6 +707,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
>         .de_type        = SUN8I_MIXER_DE2,
>         .scaler_mask    = 0xf,
>         .scanline_yuv   = 2048,
> +       .de2_fcc_alpha  = 1,
>         .ui_num         = 3,
>         .vi_num         = 1,
>  };
> @@ -716,6 +717,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
>         .de_type        = SUN8I_MIXER_DE2,
>         .scaler_mask    = 0x3,
>         .scanline_yuv   = 2048,
> +       .de2_fcc_alpha  = 1,
>         .ui_num         = 1,
>         .vi_num         = 1,
>  };
> @@ -726,6 +728,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
>         .mod_rate       = 432000000,
>         .scaler_mask    = 0xf,
>         .scanline_yuv   = 2048,
> +       .de2_fcc_alpha  = 1,
>         .ui_num         = 3,
>         .vi_num         = 1,
>  };
> @@ -736,6 +739,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
>         .mod_rate       = 297000000,
>         .scaler_mask    = 0xf,
>         .scanline_yuv   = 2048,
> +       .de2_fcc_alpha  = 1,
>         .ui_num         = 3,
>         .vi_num         = 1,
>  };
> @@ -746,6 +750,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
>         .mod_rate       = 297000000,
>         .scaler_mask    = 0x3,
>         .scanline_yuv   = 2048,
> +       .de2_fcc_alpha  = 1,
>         .ui_num         = 1,
>         .vi_num         = 1,
>  };
> @@ -766,6 +771,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {
>         .mod_rate       = 297000000,
>         .scaler_mask    = 0x3,
>         .scanline_yuv   = 2048,
> +       .de2_fcc_alpha  = 1,
>         .ui_num         = 1,
>         .vi_num         = 1,
>  };
> @@ -776,6 +782,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = {
>         .mod_rate       = 297000000,
>         .scaler_mask    = 0x1,
>         .scanline_yuv   = 1024,
> +       .de2_fcc_alpha  = 1,
>         .ui_num         = 0,
>         .vi_num         = 1,
>  };
> @@ -786,6 +793,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
>         .mod_rate       = 297000000,
>         .scaler_mask    = 0xf,
>         .scanline_yuv   = 4096,
> +       .de2_fcc_alpha  = 1,
>         .ui_num         = 3,
>         .vi_num         = 1,
>  };
> @@ -796,6 +804,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
>         .mod_rate       = 297000000,
>         .scaler_mask    = 0x3,
>         .scanline_yuv   = 2048,
> +       .de2_fcc_alpha  = 1,
>         .ui_num         = 1,
>         .vi_num         = 1,
>  };
> diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
> index d14188cdfab3..def07afd37e1 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
> +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
> @@ -176,6 +176,8 @@ enum sun8i_mixer_type {
>   *     a functional block.
>   * @de_type: sun8i_mixer_type enum representing the display engine generation.
>   * @scaline_yuv: size of a scanline for VI scaler for YUV formats.
> + * @de2_fcc_alpha: use FCC for missing DE2 VI alpha capability
> + *     Most DE2 cores has FCC. If number of VI planes is one, enable this.
>   * @map: channel map for DE variants processing YUV separately (DE33)
>   */
>  struct sun8i_mixer_cfg {
> @@ -186,6 +188,7 @@ struct sun8i_mixer_cfg {
>         unsigned long   mod_rate;
>         unsigned int    de_type;
>         unsigned int    scanline_yuv;
> +       unsigned int    de2_fcc_alpha : 1;
>         unsigned int    map[6];
>  };
>
> diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
> index 44e699910b70..8eb3f167e664 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
> @@ -48,14 +48,16 @@ static void sun8i_vi_layer_update_attributes(struct sun8i_layer *layer,
>                 val |= (state->alpha == DRM_BLEND_ALPHA_OPAQUE) ?
>                         SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_PIXEL :
>                         SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_COMBINED;
> -       } else if (mixer->cfg->vi_num == 1) {
> +       }
> +
> +       regmap_write(layer->regs,
> +                    SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), val);
> +
> +       if (mixer->cfg->de2_fcc_alpha) {
>                 regmap_write(layer->regs,
>                              SUN8I_MIXER_FCC_GLOBAL_ALPHA_REG,
>                              SUN8I_MIXER_FCC_GLOBAL_ALPHA(state->alpha >> 8));
>         }
> -
> -       regmap_write(layer->regs,
> -                    SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), val);

Should probably mention why the order is reversed here, and why it is OK.

Otherwise,

Reviewed-by: Chen-Yu Tsai <wens at kernel.org>