[PATCH 01/39] dt-bindings: display: imx: Document i.MX95 Display Controller DomainBlend

[Marek Vasut]

On 10/18/25 8:09 AM, Ying Liu wrote:

Hello Liu,

>>> BTW, I confirm that two Domain Blend Units exist in i.MX95 DC while they
>> don't
>>> exist in i.MX8qxp/qm DCs.  And, as you can see, this unit supports multiple
>>> modes, this would impact how an OS implements a display driver a lot,
>> especially
>>> Blend mode and SidebySide mode.
>>
>> There is one thing which specifically concerns me about the DB, it seems
>> to be capable of blending two inputs from different security domains, is
>> that correct ?
> 
> For now, I know nothing more than the DT binding description here, i.e.,
> two inputs are combined to one output in four modes. And, DB cannot be
> bypassed IIUC.

I see.

>>> As patch 39 shows, there are 3 interrupts - domainblend{0,1}_shdload,
>>> domainblend{0,1}_framecomplete and domainblend{0,1}_seqcomplete.
>> It seems we currently do not use either clock or interrupts on either
>> domainblend or layerblend IPs, but maybe DB and LB are different and LB
>> really has no clock/interrupts ?
> 
> If you take a look at NXP downstream kernel, it uses
> domainblend{0,1}_shdload IRQs in CRTC driver and I believe that upstream
> driver should use them too.

Can you please tell me what exactly is this IRQ signalling ?

> DB and LB are different. DB is in Display Engine, while LB is in Pixel Engine.
> This pipeline sort of tells how LD and DB are connected: LB -> ED -> DB.
> 
> LB has no interrupts.  And since it processes pixels in Pixel Engine with AXI
> CLK and it can be configured via the AHB interface of DC with CFG CLK, I'd
> say it kind of inherits AXI CLK and CFG CLK from Pixel Engine and DC
> respectively.  See the diagram in fsl,imx8qxp-dc.yaml, you'll find those
> clocks.

Thank you for the clarification. And sorry for my late reply.

-- 
Best regards,
Marek Vasut