[PATCH] arm64: dts: ti: Modify J784S4 SoC SERDES lane controller register length

[Gokul Praveen]

Hi Udit,

On 23/05/25 22:55, Kumar, Udit wrote:
> Hello Gokul
> 
> On 5/23/2025 7:19 PM, Gokul Praveen wrote:
>> Modify the J784S4 SoC SERDES lane controller register length from 0x30 
>> to 0x50
>> to enable SERDES4 registers.
>>
>> 'Fixes:9cc161a4509c2("arm64: dts: ti: Refactor J784s4 SoC files to a 
>> common
>> file")'
>> Signed-off-by: Gokul Praveen <g-praveen at ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi 
>> b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
>> index 1944616ab357..1fc0a11c5ab4 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
>> @@ -77,7 +77,7 @@ pcie1_ctrl: pcie1-ctrl at 4074 {
>>           serdes_ln_ctrl: mux-controller at 4080 {
>>               compatible = "reg-mux";
>> -            reg = <0x00004080 0x30>;
>> +            reg = <0x00004080 0x50>;
> 
> I assume above is already fixed with below patch >
> https://lore.kernel.org/all/20250423151612.48848-1-s-vadapalli@ti.com
> 
> or I am missing something

Yes,its the same fix Udit.Thanks for informing that.
> 
> 
> 
>>               #mux-control-cells = <1>;
>>               mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 
>> select */
>>                       <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */

Regards
Gokul