[PATCH] arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports

[Vignesh Raghavendra]

On 21/05/25 11:03, Wadim Egorov wrote:
> For the ICSSG PHYs to operate correctly, a 25 MHz reference clock must
> be supplied on CLKOUT0. Previously, our bootloader configured this
> clock, which is why the PRU Ethernet ports appeared to work, but the
> change never made it into the device tree.
> 

Should this patch have a Fixes tag then?

> Add clock properties to make EXT_REFCLK1.CLKOUT0 output a 25MHz clock.
> 
> Signed-off-by: Wadim Egorov <w.egorov at phytec.de>
> ---
>  arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
> index f63c101b7d61..129524eb5b91 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
> @@ -322,6 +322,8 @@ AM64X_IOPAD(0x0040, PIN_OUTPUT, 7)	/* (U21) GPMC0_AD1.GPIO0_16 */
>  &icssg0_mdio {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&icssg0_mdio_pins_default &clkout0_pins_default>;
> +	assigned-clocks = <&k3_clks 157 123>;
> +	assigned-clock-parents = <&k3_clks 157 125>;
>  	status = "okay";
>  
>  	icssg0_phy1: ethernet-phy at 1 {

-- 
Regards
Vignesh
https://ti.com/opensource