[PATCH 9/9] arm64: dts: rockchip: Enable more power domains for RK3528
Jonas Karlman
jonas at kwiboo.se
Sun May 18 15:06:56 PDT 2025
Describe device power-domains and enable the PD_RKVENC, PD_VO and PD_VPU
power-domains on RK3528.
The PD_RKVDEC is used by RKVDEC and DDRPHY CRU, and is kept disabled to
prevent a full system reset trying to read the rate of the SCMI_CLK_DDR
clock.
Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 28 +++++++++++++++++++++---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index c13a6a566164..791cb9b1e8f1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -403,7 +403,6 @@ power-domain at RK3528_PD_RKVENC {
reg = <RK3528_PD_RKVENC>;
pm_qos = <&qos_rkvenc>;
#power-domain-cells = <0>;
- status = "disabled";
};
power-domain at RK3528_PD_VO {
reg = <RK3528_PD_VO>;
@@ -417,7 +416,6 @@ power-domain at RK3528_PD_VO {
<&qos_vdpp>,
<&qos_vop>;
#power-domain-cells = <0>;
- status = "disabled";
};
power-domain at RK3528_PD_VPU {
reg = <RK3528_PD_VPU>;
@@ -431,7 +429,6 @@ power-domain at RK3528_PD_VPU {
<&qos_usb3otg>,
<&qos_vpu>;
#power-domain-cells = <0>;
- status = "disabled";
};
};
};
@@ -455,6 +452,7 @@ uart1: serial at ff9f8000 {
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 10>, <&dmac 11>;
+ power-domains = <&power RK3528_PD_RKVENC>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -467,6 +465,7 @@ uart2: serial at ffa00000 {
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 12>, <&dmac 13>;
+ power-domains = <&power RK3528_PD_VPU>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -479,6 +478,7 @@ uart3: serial at ffa08000 {
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 14>, <&dmac 15>;
+ power-domains = <&power RK3528_PD_RKVENC>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -491,6 +491,7 @@ uart4: serial at ffa10000 {
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 16>, <&dmac 17>;
+ power-domains = <&power RK3528_PD_VO>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -503,6 +504,7 @@ uart5: serial at ffa18000 {
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 18>, <&dmac 19>;
+ power-domains = <&power RK3528_PD_VPU>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -515,6 +517,7 @@ uart6: serial at ffa20000 {
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 20>, <&dmac 21>;
+ power-domains = <&power RK3528_PD_VPU>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -527,6 +530,7 @@ uart7: serial at ffa28000 {
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmac 22>, <&dmac 23>;
+ power-domains = <&power RK3528_PD_VPU>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
@@ -539,6 +543,7 @@ i2c0: i2c at ffa50000 {
clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_RKVENC>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -551,6 +556,7 @@ i2c1: i2c at ffa58000 {
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_RKVENC>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -577,6 +583,7 @@ i2c3: i2c at ffa68000 {
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -591,6 +598,7 @@ i2c4: i2c at ffa70000 {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
+ power-domains = <&power RK3528_PD_VO>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -603,6 +611,7 @@ i2c5: i2c at ffa78000 {
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -615,6 +624,7 @@ i2c6: i2c at ffa80000 {
clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -629,6 +639,7 @@ i2c7: i2c at ffa88000 {
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_xfer>;
+ power-domains = <&power RK3528_PD_VO>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -720,6 +731,7 @@ saradc: adc at ffae0000 {
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_VPU>;
resets = <&cru SRST_P_SARADC>;
reset-names = "saradc-apb";
#io-channel-cells = <1>;
@@ -740,6 +752,7 @@ gmac0: ethernet at ffbd0000 {
interrupt-names = "macirq", "eth_wake_irq";
phy-handle = <&rmii0_phy>;
phy-mode = "rmii";
+ power-domains = <&power RK3528_PD_VO>;
resets = <&cru SRST_A_MAC_VO>;
reset-names = "stmmaceth";
rockchip,grf = <&vo_grf>;
@@ -798,6 +811,7 @@ gmac1: ethernet at ffbe0000 {
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
+ power-domains = <&power RK3528_PD_VPU>;
resets = <&cru SRST_A_MAC>;
reset-names = "stmmaceth";
rockchip,grf = <&vpu_grf>;
@@ -848,6 +862,7 @@ sdhci: mmc at ffbf0000 {
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
<&emmc_strb>;
+ power-domains = <&power RK3528_PD_VPU>;
resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
<&cru SRST_T_EMMC>;
@@ -869,6 +884,7 @@ sdio0: mmc at ffc10000 {
max-frequency = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;
+ power-domains = <&power RK3528_PD_VPU>;
resets = <&cru SRST_H_SDIO0>;
reset-names = "reset";
status = "disabled";
@@ -888,6 +904,7 @@ sdio1: mmc at ffc20000 {
max-frequency = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>;
+ power-domains = <&power RK3528_PD_VPU>;
resets = <&cru SRST_H_SDIO1>;
reset-names = "reset";
status = "disabled";
@@ -908,6 +925,7 @@ sdmmc: mmc at ffc30000 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
<&sdmmc_det>;
+ power-domains = <&power RK3528_PD_VO>;
resets = <&cru SRST_H_SDMMC0>;
reset-names = "reset";
rockchip,default-sample-phase = <90>;
@@ -961,6 +979,7 @@ gpio1: gpio at ffaf0000 {
gpio-ranges = <&pinctrl 0 32 32>;
interrupt-controller;
#interrupt-cells = <2>;
+ power-domains = <&power RK3528_PD_VPU>;
};
gpio2: gpio at ffb00000 {
@@ -973,6 +992,7 @@ gpio2: gpio at ffb00000 {
gpio-ranges = <&pinctrl 0 64 32>;
interrupt-controller;
#interrupt-cells = <2>;
+ power-domains = <&power RK3528_PD_VO>;
};
gpio3: gpio at ffb10000 {
@@ -985,6 +1005,7 @@ gpio3: gpio at ffb10000 {
gpio-ranges = <&pinctrl 0 96 32>;
interrupt-controller;
#interrupt-cells = <2>;
+ power-domains = <&power RK3528_PD_VPU>;
};
gpio4: gpio at ffb20000 {
@@ -997,6 +1018,7 @@ gpio4: gpio at ffb20000 {
gpio-ranges = <&pinctrl 0 128 32>;
interrupt-controller;
#interrupt-cells = <2>;
+ power-domains = <&power RK3528_PD_RKVENC>;
};
};
};
--
2.49.0
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