[PATCH v4 11/23] iommufd/viommu: Add IOMMUFD_CMD_HW_QUEUE_ALLOC ioctl

[Tian, Kevin]

> From: Jason Gunthorpe <jgg at nvidia.com>
> Sent: Friday, May 16, 2025 12:06 AM
> 
> Do we have way to make the pinning optional?
> 
> As I understand AMD's system the iommu HW itself translates the
> base_addr through the S2 page table automatically, so it doesn't need
> pinned memory and physical addresses but just the IOVA.
> 

Though using IOVA could eliminate pinning conceptually, implementation
wise an IOMMU may not tolerate translation errors in its access to guest
queues with assumption that S2 is pinned.

@Vasant, can you help confirm?