[PATCH v3 04/12] ARM: dts: bcm6855: Add BCMBCA peripherals

[William Zhang]

> -----Original Message-----
> From: Linus Walleij <linus.walleij at linaro.org>
> Sent: Monday, May 12, 2025 5:06 AM
> To: Rob Herring <robh at kernel.org>; Krzysztof Kozlowski
> <krzk+dt at kernel.org>;
> Conor Dooley <conor+dt at kernel.org>; William Zhang
> <william.zhang at broadcom.com>; Anand Gore <anand.gore at broadcom.com>;
> Kursad Oney <kursad.oney at broadcom.com>; Florian Fainelli
> <florian.fainelli at broadcom.com>; Rafał Miłecki <rafal at milecki.pl>;
> Broadcom
> internal kernel review list <bcm-kernel-feedback-list at broadcom.com>;
> Olivia
> Mackall <olivia at selenic.com>; Ray Jui <rjui at broadcom.com>; Scott Branden
> <sbranden at broadcom.com>; Florian Fainelli <f.fainelli at gmail.com>
> Cc: devicetree at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> linux-
> crypto at vger.kernel.org; Linus Walleij <linus.walleij at linaro.org>
> Subject: [PATCH v3 04/12] ARM: dts: bcm6855: Add BCMBCA peripherals
>
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Add the first and second watchdog, GPIO, RNG, LED, DMA and
> second PL011 UART blocks for the BCM6855 based on the vendor
> files 6855_map_part.h and 6855_intr.h from the
> "bcmopen-consumer" code drop.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
> ---
>  arch/arm/boot/dts/broadcom/bcm6855.dtsi | 127
> ++++++++++++++++++++++++++++++++
>  1 file changed, 127 insertions(+)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm6855.dtsi
> b/arch/arm/boot/dts/broadcom/bcm6855.dtsi
> index
> 52915ec6f339335d87b4e50e1c03625fffb9a45d..a88c3f0fbcb037ee5c6b319334
> 15f90cb51ded2a 100644
> --- a/arch/arm/boot/dts/broadcom/bcm6855.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm6855.dtsi
> @@ -116,6 +116,103 @@ bus at ff800000 {
>  		#size-cells = <1>;
>  		ranges = <0 0xff800000 0x800000>;
>
> +		watchdog at 480 {
> +			compatible = "brcm,bcm6345-wdt";
> +			reg = <0x480 0x10>;
> +		};
> +
> +		watchdog at 4c0 {
> +			compatible = "brcm,bcm6345-wdt";
> +			reg = <0x4c0 0x10>;
> +			status = "disabled";
> +		};
> +
> +		/* GPIOs 0 .. 31 */
> +		gpio0: gpio at 500 {
> +			compatible = "brcm,bcm6345-gpio";
> +			reg = <0x500 0x04>, <0x520 0x04>;
> +			reg-names = "dirout", "dat";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			status = "disabled";
> +		};
> +
> +		/* GPIOs 32 .. 63 */
> +		gpio1: gpio at 504 {
> +			compatible = "brcm,bcm6345-gpio";
> +			reg = <0x504 0x04>, <0x524 0x04>;
> +			reg-names = "dirout", "dat";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			status = "disabled";
> +		};
> +
> +		/* GPIOs 64 .. 95 */
> +		gpio2: gpio at 508 {
> +			compatible = "brcm,bcm6345-gpio";
> +			reg = <0x508 0x04>, <0x528 0x04>;
> +			reg-names = "dirout", "dat";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			status = "disabled";
> +		};
> +
> +		/* GPIOs 96 .. 127 */
> +		gpio3: gpio at 50c {
> +			compatible = "brcm,bcm6345-gpio";
> +			reg = <0x50c 0x04>, <0x52c 0x04>;
> +			reg-names = "dirout", "dat";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			status = "disabled";
> +		};
> +
> +		/* GPIOs 128 .. 159 */
> +		gpio4: gpio at 510 {
> +			compatible = "brcm,bcm6345-gpio";
> +			reg = <0x510 0x04>, <0x530 0x04>;
> +			reg-names = "dirout", "dat";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			status = "disabled";
> +		};
> +
> +		/* GPIOs 160 .. 191 */
> +		gpio5: gpio at 514 {
> +			compatible = "brcm,bcm6345-gpio";
> +			reg = <0x514 0x04>, <0x534 0x04>;
> +			reg-names = "dirout", "dat";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			status = "disabled";
> +		};
> +
> +		/* GPIOs 192 .. 223 */
> +		gpio6: gpio at 518 {
> +			compatible = "brcm,bcm6345-gpio";
> +			reg = <0x518 0x04>, <0x538 0x04>;
> +			reg-names = "dirout", "dat";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			status = "disabled";
> +		};
> +
> +		/* GPIOs 224 .. 255 */
> +		gpio7: gpio at 51c {
> +			compatible = "brcm,bcm6345-gpio";
> +			reg = <0x51c 0x04>, <0x53c 0x04>;
> +			reg-names = "dirout", "dat";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			status = "disabled";
> +		};
> +
> +		rng at b80 {
> +			compatible = "brcm,iproc-rng200";
> +			reg = <0xb80 0x28>;
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
>  		hsspi: spi at 1000 {
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> @@ -143,6 +240,27 @@ nandcs: nand at 0 {
>  			};
>  		};
>
> +		leds: led-controller at 3000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "brcm,bcm63138-leds";
> +			reg = <0x3000 0xdc>;
> +			status = "disabled";
> +		};
> +
> +		pl081_dma: dma-controller at 11000 {
> +			compatible = "arm,pl081", "arm,primecell";
> +			// The magic B105F00D info is missing
> +			arm,primecell-periphid = <0x00041081>;
> +			reg = <0x11000 0x1000>;
> +			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +			memcpy-burst-size = <256>;
> +			memcpy-bus-width = <32>;
> +			clocks = <&periph_clk>;
> +			clock-names = "apb_pclk";
> +			#dma-cells = <2>;
> +		};
> +
>  		uart0: serial at 12000 {
>  			compatible = "arm,pl011", "arm,primecell";
>  			reg = <0x12000 0x1000>;
> @@ -151,5 +269,14 @@ uart0: serial at 12000 {
>  			clock-names = "uartclk", "apb_pclk";
>  			status = "disabled";
>  		};
> +
> +		uart1: serial at 13000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x13000 0x1000>;
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&uart_clk>, <&uart_clk>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
>  	};
>  };
>
> --
> 2.49.0

Reviewed-by: William Zhang <william.zhang at broadcom.com>
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