[PATCH 3/3] ARM: dts: vt8500: Add serial flash controller and its clock
Alexey Charkov
alchark at gmail.com
Sat May 10 12:42:23 PDT 2025
The serial flash controller resides at the same MMIO address in all known
VIA/WonderMedia SoCs, and its clock uses the same enable bit and divisor
reg on all SoCs, feeding off PLL B.
Add respective DT nodes using SoC specific compatibles for the controller
to make it future proof in case any differences in behavior are discovered
later on.
All known boards boot from SPI NOR flash, so their flash chips are at CS0
and mapped by the boot ROM at the end of their CPU address space. Add
respective DT nodes in board-specific dts files too.
Signed-off-by: Alexey Charkov <alchark at gmail.com>
---
arch/arm/boot/dts/vt8500/vt8500-bv07.dts | 37 ++++++++++++++++++++++++++++
arch/arm/boot/dts/vt8500/vt8500.dtsi | 34 +++++++++++++++++++++++++
arch/arm/boot/dts/vt8500/wm8505-ref.dts | 37 ++++++++++++++++++++++++++++
arch/arm/boot/dts/vt8500/wm8505.dtsi | 21 ++++++++++++++++
arch/arm/boot/dts/vt8500/wm8650-mid.dts | 37 ++++++++++++++++++++++++++++
arch/arm/boot/dts/vt8500/wm8650.dtsi | 21 ++++++++++++++++
arch/arm/boot/dts/vt8500/wm8750-apc8750.dts | 37 ++++++++++++++++++++++++++++
arch/arm/boot/dts/vt8500/wm8750.dtsi | 21 ++++++++++++++++
arch/arm/boot/dts/vt8500/wm8850-w70v2.dts | 37 ++++++++++++++++++++++++++++
arch/arm/boot/dts/vt8500/wm8850.dtsi | 21 ++++++++++++++++
arch/arm/boot/dts/vt8500/wm8950-apc-rock.dts | 37 ++++++++++++++++++++++++++++
11 files changed, 340 insertions(+)
diff --git a/arch/arm/boot/dts/vt8500/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500/vt8500-bv07.dts
index 38a2da5e2c5d64477f04e1da9d98cb97be0d95e4..c3c5ba3ac014cc49bee8c2b9e6c7b25225d4d5fe 100644
--- a/arch/arm/boot/dts/vt8500/vt8500-bv07.dts
+++ b/arch/arm/boot/dts/vt8500/vt8500-bv07.dts
@@ -30,6 +30,43 @@ timing0: timing-800x480 {
};
};
+&sflash {
+ status = "okay";
+
+ flash at 0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "U-boot";
+ reg = <0 0x50000>;
+ read-only;
+ };
+
+ partition at 1 {
+ label = "U-boot environment 1";
+ reg = <0x50000 0x10000>;
+ };
+
+ partition at 2 {
+ label = "U-boot environment 2";
+ reg = <0x60000 0x10000>;
+ };
+
+ partition at 3 {
+ label = "W-load";
+ reg = <0x70000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/vt8500/vt8500.dtsi b/arch/arm/boot/dts/vt8500/vt8500.dtsi
index 2ba021585d4889f29777a12473964c29f999f3a0..7ea115576c69b517cb2a08206638062f22c976a0 100644
--- a/arch/arm/boot/dts/vt8500/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500/vt8500.dtsi
@@ -74,6 +74,19 @@ ref24: ref24M {
clock-frequency = <24000000>;
};
+ ref25: clock-25000000 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ pllb: clock at 204 {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-pll-clock";
+ clocks = <&ref25>;
+ reg = <0x204>;
+ };
+
clkuart0: uart0 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
@@ -105,6 +118,15 @@ clkuart3: uart3 {
enable-reg = <0x250>;
enable-bit = <4>;
};
+
+ clksf: clock {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x314>;
+ enable-reg = <0x254>;
+ enable-bit = <23>;
+ };
};
};
@@ -114,6 +136,18 @@ timer at d8130100 {
interrupts = <36>;
};
+ sflash: spi-nor-controller at d8002000 {
+ compatible = "via,vt8500-sflash";
+ reg = <0xd8002000 0x400>,
+ <0xff800000 0x800000>,
+ <0xef800000 0x800000>;
+ reg-names = "io", "chip0-mmap", "chip1-mmap";
+ clocks = <&clksf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
usb at d8007900 {
compatible = "via,vt8500-ehci";
reg = <0xd8007900 0x200>;
diff --git a/arch/arm/boot/dts/vt8500/wm8505-ref.dts b/arch/arm/boot/dts/vt8500/wm8505-ref.dts
index 8ce9e2ef0a81097e7143a5392ee5b42bf8028ec1..b037f9d919fb51a527f35276e2b8601f3f3d8505 100644
--- a/arch/arm/boot/dts/vt8500/wm8505-ref.dts
+++ b/arch/arm/boot/dts/vt8500/wm8505-ref.dts
@@ -30,6 +30,43 @@ timing0: timing-800x480 {
};
};
+&sflash {
+ status = "okay";
+
+ flash at 0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "U-boot";
+ reg = <0 0x50000>;
+ read-only;
+ };
+
+ partition at 1 {
+ label = "U-boot environment 1";
+ reg = <0x50000 0x10000>;
+ };
+
+ partition at 2 {
+ label = "U-boot environment 2";
+ reg = <0x60000 0x10000>;
+ };
+
+ partition at 3 {
+ label = "W-load";
+ reg = <0x70000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/vt8500/wm8505.dtsi b/arch/arm/boot/dts/vt8500/wm8505.dtsi
index 99c064c916b2279797f71261ca9306e9dcd4bbd8..bf9ba4e99f86d1bf41c4e4bfe8b4f71ad162be4f 100644
--- a/arch/arm/boot/dts/vt8500/wm8505.dtsi
+++ b/arch/arm/boot/dts/vt8500/wm8505.dtsi
@@ -203,6 +203,15 @@ clksdhc: sdhc {
enable-reg = <0x254>;
enable-bit = <18>;
};
+
+ clksf: clock {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x314>;
+ enable-reg = <0x254>;
+ enable-bit = <23>;
+ };
};
};
@@ -212,6 +221,18 @@ timer at d8130100 {
interrupts = <36>;
};
+ sflash: spi-nor-controller at d8002000 {
+ compatible = "wm,wm8505-sflash";
+ reg = <0xd8002000 0x400>,
+ <0xff800000 0x800000>,
+ <0xef800000 0x800000>;
+ reg-names = "io", "chip0-mmap", "chip1-mmap";
+ clocks = <&clksf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
usb at d8007100 {
compatible = "via,vt8500-ehci";
reg = <0xd8007100 0x200>;
diff --git a/arch/arm/boot/dts/vt8500/wm8650-mid.dts b/arch/arm/boot/dts/vt8500/wm8650-mid.dts
index 7977b6c1e8ebf215df210dee703e470b9159d329..d3c8b7b99706603bab5aa8dad1165edb3763c2f6 100644
--- a/arch/arm/boot/dts/vt8500/wm8650-mid.dts
+++ b/arch/arm/boot/dts/vt8500/wm8650-mid.dts
@@ -31,6 +31,43 @@ timing0: timing-800x480 {
};
};
+&sflash {
+ status = "okay";
+
+ flash at 0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "U-boot";
+ reg = <0 0x50000>;
+ read-only;
+ };
+
+ partition at 1 {
+ label = "U-boot environment 1";
+ reg = <0x50000 0x10000>;
+ };
+
+ partition at 2 {
+ label = "U-boot environment 2";
+ reg = <0x60000 0x10000>;
+ };
+
+ partition at 3 {
+ label = "W-load";
+ reg = <0x70000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/vt8500/wm8650.dtsi b/arch/arm/boot/dts/vt8500/wm8650.dtsi
index 0d6c7bd87f7dcce0eef056d04c38ab1de5d52639..972b61d2437b1da9ce765b65f844872e8df4da1d 100644
--- a/arch/arm/boot/dts/vt8500/wm8650.dtsi
+++ b/arch/arm/boot/dts/vt8500/wm8650.dtsi
@@ -175,6 +175,15 @@ clksdhc: sdhc {
enable-reg = <0x254>;
enable-bit = <18>;
};
+
+ clksf: clock {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x314>;
+ enable-reg = <0x254>;
+ enable-bit = <23>;
+ };
};
};
@@ -184,6 +193,18 @@ timer at d8130100 {
interrupts = <36>;
};
+ sflash: spi-nor-controller at d8002000 {
+ compatible = "wm,wm8650-sflash";
+ reg = <0xd8002000 0x400>,
+ <0xff800000 0x800000>,
+ <0xef800000 0x800000>;
+ reg-names = "io", "chip0-mmap", "chip1-mmap";
+ clocks = <&clksf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
usb at d8007900 {
compatible = "via,vt8500-ehci";
reg = <0xd8007900 0x200>;
diff --git a/arch/arm/boot/dts/vt8500/wm8750-apc8750.dts b/arch/arm/boot/dts/vt8500/wm8750-apc8750.dts
index 136e812bc1e498d48c7fc61154bc66a48888b117..4465946cfe44e82db1cad14c1f81237e1ccc0e67 100644
--- a/arch/arm/boot/dts/vt8500/wm8750-apc8750.dts
+++ b/arch/arm/boot/dts/vt8500/wm8750-apc8750.dts
@@ -24,6 +24,43 @@ i2c: i2c {
};
};
+&sflash {
+ status = "okay";
+
+ flash at 0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "U-boot";
+ reg = <0 0x50000>;
+ read-only;
+ };
+
+ partition at 1 {
+ label = "U-boot environment 1";
+ reg = <0x50000 0x10000>;
+ };
+
+ partition at 2 {
+ label = "U-boot environment 2";
+ reg = <0x60000 0x10000>;
+ };
+
+ partition at 3 {
+ label = "W-load";
+ reg = <0x70000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/vt8500/wm8750.dtsi b/arch/arm/boot/dts/vt8500/wm8750.dtsi
index 0158c0ba5dd110957eac38775d3bf3ebd2ab4154..d6b4e4463fae1e8a0a3cf0feecce7125b4a67f5c 100644
--- a/arch/arm/boot/dts/vt8500/wm8750.dtsi
+++ b/arch/arm/boot/dts/vt8500/wm8750.dtsi
@@ -240,6 +240,15 @@ clki2c1: i2c1clk {
enable-reg = <0x250>;
enable-bit = <9>;
};
+
+ clksf: clock {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x314>;
+ enable-reg = <0x254>;
+ enable-bit = <23>;
+ };
};
};
@@ -256,6 +265,18 @@ timer at d8130100 {
interrupts = <36>;
};
+ sflash: spi-nor-controller at d8002000 {
+ compatible = "wm,wm8750-sflash";
+ reg = <0xd8002000 0x400>,
+ <0xff800000 0x800000>,
+ <0xef800000 0x800000>;
+ reg-names = "io", "chip0-mmap", "chip1-mmap";
+ clocks = <&clksf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
usb at d8007900 {
compatible = "via,vt8500-ehci";
reg = <0xd8007900 0x200>;
diff --git a/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts b/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts
index 5d409323b10cb94a5694722de1e31cff5be390ce..d2638a204579d3dff477bb7f458438037e08019b 100644
--- a/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts
+++ b/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts
@@ -42,6 +42,43 @@ timing0: timing-800x480 {
};
};
+&sflash {
+ status = "okay";
+
+ flash at 0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "U-boot";
+ reg = <0 0x50000>;
+ read-only;
+ };
+
+ partition at 1 {
+ label = "U-boot environment 1";
+ reg = <0x50000 0x10000>;
+ };
+
+ partition at 2 {
+ label = "U-boot environment 2";
+ reg = <0x60000 0x10000>;
+ };
+
+ partition at 3 {
+ label = "W-load";
+ reg = <0x70000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/vt8500/wm8850.dtsi b/arch/arm/boot/dts/vt8500/wm8850.dtsi
index c4bfb4d30aad0358b39cbf30edf0c63e32167bbd..6837198de2508536eef52537a7f451679d36c38b 100644
--- a/arch/arm/boot/dts/vt8500/wm8850.dtsi
+++ b/arch/arm/boot/dts/vt8500/wm8850.dtsi
@@ -217,6 +217,15 @@ clksdhc: sdhc {
enable-reg = <0x250>;
enable-bit = <0>;
};
+
+ clksf: clock {
+ #clock-cells = <0>;
+ compatible = "via,vt8500-device-clock";
+ clocks = <&pllb>;
+ divisor-reg = <0x314>;
+ enable-reg = <0x254>;
+ enable-bit = <23>;
+ };
};
};
@@ -243,6 +252,18 @@ timer at d8130100 {
interrupts = <36>;
};
+ sflash: spi-nor-controller at d8002000 {
+ compatible = "wm,wm8850-sflash";
+ reg = <0xd8002000 0x400>,
+ <0xff800000 0x800000>,
+ <0xef800000 0x800000>;
+ reg-names = "io", "chip0-mmap", "chip1-mmap";
+ clocks = <&clksf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
usb at d8007900 {
compatible = "via,vt8500-ehci";
reg = <0xd8007900 0x200>;
diff --git a/arch/arm/boot/dts/vt8500/wm8950-apc-rock.dts b/arch/arm/boot/dts/vt8500/wm8950-apc-rock.dts
index 58b3c8deb4f20ae072bf1381f1dfa5e5adeb414a..647fdcccdbbd680276af1fa30363e09bbeb5ad16 100644
--- a/arch/arm/boot/dts/vt8500/wm8950-apc-rock.dts
+++ b/arch/arm/boot/dts/vt8500/wm8950-apc-rock.dts
@@ -16,6 +16,43 @@ memory at 0 {
};
};
+&sflash {
+ status = "okay";
+
+ flash at 0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition at 0 {
+ label = "U-boot";
+ reg = <0 0x50000>;
+ read-only;
+ };
+
+ partition at 1 {
+ label = "U-boot environment 1";
+ reg = <0x50000 0x10000>;
+ };
+
+ partition at 2 {
+ label = "U-boot environment 2";
+ reg = <0x60000 0x10000>;
+ };
+
+ partition at 3 {
+ label = "W-load";
+ reg = <0x70000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
--
2.49.0
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