[PATCH v2 4/5] arm64: dts: rockchip: reference u2phy1 as clock on RK3576

[Nicolas Frattaroli]

The rockchip,dwc3 binding states that the utmi clock may be referenced
by the controller. Until now, the u2phy1's clock output had no
references to it in the SoC device tree. It's not known if this caused
any real-world issues, but it may have allowed the USB controller to
potentially do operations that depend on the utmi clock while it is not
enabled, leading to hard-to-reproduce race conditions during bootup.

Reference the u2phy1 output clock in its corresponding USB controller as
an utmi clock. This effectively increases the enable count of the
usb480m_phy1 clock in Linux on my system from a deviceless 1 to a 2 with
the USB controller as a named user.

Fixes: 23ec57a32da4 ("arm64: dts: rockchip: add usb related nodes for rk3576")
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli at collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3576.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index ddc92ccc530d6757660971f0a609b5127784bb04..fa4ff44ec48b4b8759b7d4d1c752afd3333fd43d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -480,8 +480,9 @@ usb_drd1_dwc3: usb at 23400000 {
 			reg = <0x0 0x23400000 0x0 0x400000>;
 			clocks = <&cru CLK_REF_USB3OTG1>,
 				 <&cru CLK_SUSPEND_USB3OTG1>,
-				 <&cru ACLK_USB3OTG1>;
-			clock-names = "ref_clk", "suspend_clk", "bus_clk";
+				 <&cru ACLK_USB3OTG1>,
+				 <&u2phy1>;
+			clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi";
 			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 			power-domains = <&power RK3576_PD_PHP>;
 			resets = <&cru SRST_A_USB3OTG1>;

-- 
2.49.0