[PATCH 2/2] WIP: arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile
Sirius Wang
sirius.wang at mediatek.com
Mon May 5 05:15:46 PDT 2025
MT8189 is a SoC based on 64bit ARMv8 architecture. It contains 6 CA55
and 2 CA78 cores. MT8189 share many HW IP with MT8188 series.
We add basic chip support for MediaTek MT8189 on evaluation board.
BUG=b:387230785
TEST=emerge-skywalker chromeos-kernel-6_6
Signed-off-by: Sirius Wang <sirius.wang at mediatek.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 +
arch/arm64/boot/dts/mediatek/mt8189.dtsi | 441 ++++++++++++++++++++
3 files changed, 462 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 3aa06476c6c0..ad2ac9e1bb79 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8189-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8189-evb.dts b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
new file mode 100644
index 000000000000..e5d9ce1b8e61
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189-evb.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Author: Sirius Wang <sirius.wang at mediatek.com>
+ */
+/dts-v1/;
+#include "mt8189.dtsi"
+
+/ {
+ model = "MediaTek MT8189 evaluation board";
+ compatible = "mediatek,mt8189-evb", "mediatek,mt8189";
+
+ chosen: chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
new file mode 100644
index 000000000000..de59d858bcf3
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi
@@ -0,0 +1,441 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/ti-syscon.h>
+
+/ {
+ compatible = "mediatek,mt8189";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x000>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu at 200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu at 300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu at 400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x400>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5: cpu at 500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x500>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <742>;
+ cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff_l &system_vcore &s2idle>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6: cpu at 600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x600>;
+ enable-method = "psci";
+ clock-frequency = <3000000000>;
+ capacity-dmips-mhz = <958>;
+ cpu-idle-states = <&cpuoff_m &clusteroff_m &mcusysoff_m &system_vcore &s2idle>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu at 700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x700>;
+ enable-method = "psci";
+ clock-frequency = <3000000000>;
+ capacity-dmips-mhz = <958>;
+ cpu-idle-states = <&cpuoff_m &clusteroff_m &mcusysoff_m &system_vcore &s2idle>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ core4 {
+ cpu = <&cpu4>;
+ };
+ core5 {
+ cpu = <&cpu5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ cpuoff_l: cpuoff-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <97>;
+ exit-latency-us = <252>;
+ min-residency-us = <6710>;
+ };
+
+ cpuoff_m: cpuoff-m {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <53>;
+ exit-latency-us = <143>;
+ min-residency-us = <2120>;
+ };
+
+ cpuoff_b: cpuoff-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <40>;
+ exit-latency-us = <107>;
+ min-residency-us = <2580>;
+ };
+
+ clusteroff_l: clusteroff-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <109>;
+ exit-latency-us = <325>;
+ min-residency-us = <6710>;
+ };
+
+ clusteroff_m: clusteroff-m {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <59>;
+ exit-latency-us = <188>;
+ min-residency-us = <2120>;
+ };
+
+ clusteroff_b: clusteroff-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010001>;
+ local-timer-stop;
+ entry-latency-us = <43>;
+ exit-latency-us = <138>;
+ min-residency-us = <2580>;
+ };
+
+ mcusysoff_l: mcusysoff-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x02010007>;
+ local-timer-stop;
+ entry-latency-us = <1357>;
+ exit-latency-us = <835>;
+ min-residency-us = <6710>;
+ };
+
+ mcusysoff_m: mcusysoff-m {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x02010007>;
+ local-timer-stop;
+ entry-latency-us = <1202>;
+ exit-latency-us = <679>;
+ min-residency-us = <2120>;
+ };
+
+ mcusysoff_b: mcusysoff-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x02010007>;
+ local-timer-stop;
+ entry-latency-us = <1143>;
+ exit-latency-us = <611>;
+ min-residency-us = <2580>;
+ };
+
+ system_vcore: system-vcore {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x020100ff>;
+ local-timer-stop;
+ entry-latency-us = <940>;
+ exit-latency-us = <3500>;
+ min-residency-us = <35200>;
+ };
+
+ s2idle: s2idle {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x020180ff>;
+ local-timer-stop;
+ entry-latency-us = <10000>;
+ exit-latency-us = <10000>;
+ min-residency-us = <4294967295>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_0>;
+ cache-unified;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_0>;
+ cache-unified;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ clocks {
+ clk_null: clk-null {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ clk32k: clk32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ };
+
+ clk26m: clk26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk13m: clk13m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13000000>;
+ };
+
+ ulposc: ulposc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <520000000>;
+ };
+
+ ulposc3: ulposc3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk104m: clk104m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <104000000>;
+ };
+ };
+
+ memory: memory {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0xC0000000>;
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-frequency = <13000000>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+ performance: performance-controller at 11bc10 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
+ gic: interrupt-controller at c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0xc000000 0 0x40000>, /* distributor */
+ <0 0xc040000 0 0x200000>; /* redistributor */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ uart0: serial at 11001000 {
+ compatible = "mediatek,mt6577-uart";
+ reg = <0 0x11001000 0 0x1000>;
+ interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>;
+ clock-names = "baud", "bus";
+ uart-line = <0>;
+ };
+ };
+};
--
2.45.2
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