[PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space

[Nishanth Menon]

Hi Siddharth Vadapalli,

On Tue, 22 Apr 2025 17:30:35 +0530, Siddharth Vadapalli wrote:
> The Cadence PCIe Controllers in TI's K3 SoCs namely:
> AM64, J7200, J721E, J721S2 (AM68), J722S, J742S2 and J784S4 (AM69)
> support two address regions:
> 1. 128 MB address region in the 32-bit address space
> 2. 4 GB address region in the 64-bit address space
> 
> Currently, the 128 MB region in the 32-bit address space is enabled in
> the device-tree. This might be suitable for most of the use-cases, but
> for those use-cases requiring larger address regions than 128 MB it is
> necessary to switch to the 64-bit address space with the 4 GB address
> region. This series implements the corresponding device-tree changes to
> support the 4 GB address region as the default configuration. Existing
> use-cases should continue to work without any regression.
> 
> [...]

I have applied the following to branch ti-k3-dts-next on [1].

NOTE: I have ignored the checkpatch warning on long lines since the
documentation added in the context of the line makes more sense than splitting
it up.

Thank you!

[1/7] arm64: dts: ti: k3-am64-main: switch to 64-bit address space for PCIe0
      commit: 1159f911435b9371575d9956bb5aef579265d29a
[2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1
      commit: 46e3d7d7048872ffb90aa25e360b975dc1c3e28b
[3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1
      commit: 1025003a1e068a25b35e1dbb39cad18e23278c0f
[4/7] arm64: dts: ti: k3-j721e-main: switch to 64-bit address space for PCIe0 and PCIe1
      commit: f0f78192d3b3b3c3c935de0d681e7bf2117bbb13
[5/7] arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for PCIe1
      commit: 5a765365c689b90ea81f651a43bc30cd9c9c4ed8
[6/7] arm64: dts: ti: k3-j722s-main: switch to 64-bit address space for PCIe0
      commit: 0fde00328cf8245bf498349a696ba22d6a4a1916
[7/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address space for PCIe0 and PCIe1
      commit: b1f9ec6545c6423e106f0aeddc3b8651b5ad116c

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
-- 
Regards,
Nishanth Menon
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