[PATCH v2 01/13] dt-bindings: pci: apple,pcie: Add t6020 compatible string

[Rob Herring]

On Tue, Mar 25, 2025 at 11:49 AM Marc Zyngier <maz at kernel.org> wrote:
>
> On Tue, 25 Mar 2025 15:41:15 +0000,
> Mark Kettenis <mark.kettenis at xs4all.nl> wrote:
> >
> > > Date: Tue, 25 Mar 2025 11:02:30 +0000
> > > From: Marc Zyngier <maz at kernel.org>
> >
> > Hi Marc,
> >
> > > Hi Mark,
> > >
> > > On Tue, 25 Mar 2025 10:50:18 +0000,
> > > Mark Kettenis <mark.kettenis at xs4all.nl> wrote:
> > > >
> > > > > From: Marc Zyngier <maz at kernel.org>
> > > > > Date: Tue, 25 Mar 2025 10:25:58 +0000
> > > >
> > > > > @@ -50,6 +55,10 @@ properties:
> > > > >        - const: port1
> > > > >        - const: port2
> > > > >        - const: port3
> > > > > +      - const: phy0
> > > > > +      - const: phy1
> > > > > +      - const: phy2
> > > > > +      - const: phy3
> > >
> > > Do we need to make this t6020 specific?
> > >
> > > Obviously, separate PHY registers do not make much sense before t6020,
> > > but I couldn't find a way to describe that. I don't even know if
> > > that's a desirable outcome.
> >
> > I don't think there is a way to do that other than creating a separate
> > binding for t6020.  But I'm far from a dt-schema expert.  Maybe robh
> > has some advice here.
>
> Huh, I'd rather not create another binding. The only thing this would
> buy us is a stricter checking of the register ranges.  But it isn't
> like this block is going to find its way in random HW, and this is
> only described in a handful of core dtsi files anyway.
>
> Unless someone screams (and provides a reasonable alternative), I will
> leave it as is.

The simplest thing to do here is (under the 'allOf'):

if:
  properties:
    compatible:
      contains:
        const: apple,t6020-pcie
then:
  properties:
    reg-names:
      minItems: 10

If/when we start having different number of ports with phy entries,
then it gets messy and each variant has to list out the names or we
give up on defining the order.

Rob