[PATCH v6 2/7] dt-bindings: memory-controllers: Add STM32 Octo Memory Manager controller
Patrice CHOTARD
patrice.chotard at foss.st.com
Mon Mar 24 06:29:06 PDT 2025
On 3/21/25 15:02, Rob Herring wrote:
> On Fri, Mar 21, 2025 at 10:32:22AM +0100, Patrice Chotard wrote:
>> Add bindings for STM32 Octo Memory Manager (OMM) controller.
>>
>> OMM manages:
>> - the muxing between 2 OSPI busses and 2 output ports.
>> There are 4 possible muxing configurations:
>> - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
>> output is on port 2
>> - OSPI1 and OSPI2 are multiplexed over the same output port 1
>> - swapped mode (no multiplexing), OSPI1 output is on port 2,
>> OSPI2 output is on port 1
>> - OSPI1 and OSPI2 are multiplexed over the same output port 2
>> - the split of the memory area shared between the 2 OSPI instances.
>> - chip select selection override.
>> - the time between 2 transactions in multiplexed mode.
>>
>> Signed-off-by: Patrice Chotard <patrice.chotard at foss.st.com>
>> ---
>> .../memory-controllers/st,stm32mp25-omm.yaml | 227 +++++++++++++++++++++
>> 1 file changed, 227 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..2f8fa7569009369ebd077e4c6f4ab409a91838a5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml
>> @@ -0,0 +1,227 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: STM32 Octo Memory Manager (OMM)
>> +
>> +maintainers:
>> + - Patrice Chotard <patrice.chotard at foss.st.com>
>> +
>> +description: |
>> + The STM32 Octo Memory Manager is a low-level interface that enables an
>> + efficient OCTOSPI pin assignment with a full I/O matrix (before alternate
>> + function map) and multiplex of single/dual/quad/octal SPI interfaces over
>> + the same bus. It Supports up to:
>> + - Two single/dual/quad/octal SPI interfaces
>> + - Two ports for pin assignment
>> +
>> +properties:
>> + compatible:
>> + const: st,stm32mp25-omm
>> +
>> + "#address-cells":
>> + const: 2
>> +
>> + "#size-cells":
>> + const: 1
>> +
>> + ranges:
>> + description: |
>> + Reflects the memory layout with four integer values per OSPI instance.
>
> You say 4 here...
Hi Rob,
Yes, each range is composed by 4 integers:
ranges = <0 0 0x40430000 0x400>,
<1 0 0x40440000 0x400>;
And we got 2 ranges entry, one for each OSPI instance.
Maybe to avoid confusion, i can just update the description as following:
+ description: |
+ Reflects the memory layout per OSPI instance.
Is it ok for you ?
>
>> + Format:
>> + <chip-select> 0 <registers base address> <size>
>> + minItems: 2
>> + maxItems: 2
>
> And 2 here. I'm confused. From the example it doesn't look like you are
see my answer just above.
> using ranges correctly. If you are parsing it yourself, that's wrong.
> More below.
>
>> +
>> + reg:
>> + items:
>> + - description: OMM registers
>> + - description: OMM memory map area
>> +
>> + reg-names:
>> + items:
>> + - const: regs
>> + - const: memory_map
>> +
>> + memory-region:
>> + description: |
>> + Memory region shared between the 2 OCTOSPI instance.
>> + One or two phandle to a node describing a memory mapped region
>> + depending of child number.
>> + minItems: 1
>> + maxItems: 2
>> +
>> + memory-region-names:
>> + description: |
>
> Don't need '|'.
Ok
>
>> + OCTOSPI instance's name to which memory region is associated
>
> That doesn't really tell me anything.
We must identify to which OSPI instance the memory region belongs to.
This is needed to configure/check the memory region area split between
these 2 OSPI instance.
Must i update the description ?
>
>> + items:
>> + enum: [ospi1, ospi2]
>> + minItems: 1
>> + maxItems: 2
>> +
>> + clocks:
>> + minItems: 3
>> + maxItems: 3
>> +
>> + clock-names:
>> + items:
>> + enum: [omm, ospi1, ospi2]
>
> Define the order.
Ok, i will update as following:
clock-names:
items:
- const: omm
- const: ospi1
- const: ospi2
>
>> + minItems: 3
>> + maxItems: 3
>> +
>> + resets:
>> + minItems: 3
>> + maxItems: 3
>> +
>> + reset-names:
>> + items:
>> + enum: [omm, ospi1, ospi2]
>
> Define the order.
ok, will update as below:
reset-names:
items:
- const: omm
- const: ospi1
- const: ospi2
>
>> + minItems: 3
>> + maxItems: 3
>> +
>> + access-controllers:
>> + maxItems: 1
>> +
>> + st,syscfg-amcr:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description: |
>> + The Address Mapping Control Register (AMCR) is used to split the 256MB
>> + memory map area shared between the 2 OSPI instance. The Octo Memory
>> + Manager sets the AMCR depending of the memory-region configuration.
>> + The memory split bitmask description is:
>> + - 000: OCTOSPI1 (256 Mbytes), OCTOSPI2 unmapped
>> + - 001: OCTOSPI1 (192 Mbytes), OCTOSPI2 (64 Mbytes)
>> + - 010: OCTOSPI1 (128 Mbytes), OCTOSPI2 (128 Mbytes)
>> + - 011: OCTOSPI1 (64 Mbytes), OCTOSPI2 (192 Mbytes)
>> + - 1xx: OCTOSPI1 unmapped, OCTOSPI2 (256 Mbytes)
>> + items:
>> + - description: phandle to syscfg
>> + - description: register offset within syscfg
>> + - description: register bitmask for memory split
>> +
>> + st,omm-req2ack-ns:
>> + description: |
>
> Don't need '|'.
ok
>
>> + In multiplexed mode (MUXEN = 1), this field defines the time in
>> + nanoseconds between two transactions.
>> + default: 0
>> +
>> + st,omm-cssel-ovr:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description: |
>> + Configure the chip select selector override for the 2 OCTOSPIs.
>> + - 0: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS1
>> + - 1: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS1
>> + - 2: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS2
>> + - 3: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS2
>> + minimum: 0
>> + maximum: 3
>> + default: 0
>> +
>> + st,omm-mux:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description: |
>> + Configure the muxing between the 2 OCTOSPIs busses and the 2 output ports.
>> + - 0: direct mode
>> + - 1: mux OCTOSPI1 and OCTOSPI2 to port 1
>> + - 2: swapped mode
>> + - 3: mux OCTOSPI1 and OCTOSPI2 to port 2
>> + minimum: 0
>> + maximum: 3
>> + default: 0
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> +patternProperties:
>> + ^spi@[a-f0-9]+$:
Due to your comments below, schema will be updated as following:
^spi@[0-9]:
>> + type: object
>> + $ref: /schemas/spi/st,stm32mp25-ospi.yaml#
>> + description: Required spi child node
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - "#address-cells"
>> + - "#size-cells"
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> + - st,syscfg-amcr
>> + - ranges
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/st,stm32mp25-rcc.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/reset/st,stm32mp25-rcc.h>
>> + ommanager at 40500000 {
>> + compatible = "st,stm32mp25-omm";
>> + reg = <0x40500000 0x400>, <0x60000000 0x10000000>;
>> + reg-names = "regs", "memory_map";
>> + ranges = <0 0 0x40430000 0x400>,
>> + <1 0 0x40440000 0x400>;
>
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> +
>
>> + spi at 40430000 {
>
> ranges is okay, but the unit-address is wrong here. It should be based
> on reg below. So 'spi at 0' or 'spi at 0,0' since chip select is a distinct
> field. It's up to you, but you need to define the format in the schema.
Ok i will use spi at 0
>
>> + compatible = "st,stm32mp25-ospi";
>> + reg = <0 0 0x400>;
>> + memory-region = <&mm_ospi1>;
>> + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
>> + dmas = <&hpdma 2 0x62 0x00003121 0x0>,
>> + <&hpdma 2 0x42 0x00003112 0x0>;
>> + dma-names = "tx", "rx";
>> + clocks = <&scmi_clk CK_SCMI_OSPI1>;
>> + resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>;
>> + access-controllers = <&rifsc 74>;
>> + power-domains = <&CLUSTER_PD>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + st,syscfg-dlyb = <&syscfg 0x1000>;
>> + };
>> +
>> + spi at 40440000 {
>
> spi at 1,0
ok, will use spi at 1
Thanks
Patrice
>
>> + compatible = "st,stm32mp25-ospi";
>> + reg = <1 0 0x400>;
>> + memory-region = <&mm_ospi1>;
>> + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
>> + dmas = <&hpdma 3 0x62 0x00003121 0x0>,
>> + <&hpdma 3 0x42 0x00003112 0x0>;
>> + dma-names = "tx", "rx";
>> + clocks = <&scmi_clk CK_KER_OSPI2>;
>> + resets = <&scmi_reset RST_SCMI_OSPI2>, <&scmi_reset RST_SCMI_OSPI1DLL>;
>> + access-controllers = <&rifsc 75>;
>> + power-domains = <&CLUSTER_PD>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + st,syscfg-dlyb = <&syscfg 0x1000>;
>> + };
>> + };
>>
>> --
>> 2.25.1
>>
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