[PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support

[Marc Zyngier]

On Thu, 20 Mar 2025 09:57:13 +0000,
Peter Chen <peter.chen at cixtech.com> wrote:
> 
> On 25-03-20 09:36:37, Marc Zyngier wrote:
> > Peter Chen <peter.chen at cixtech.com> wrote:
> > >
> > > +     pmu-a520 {
> > > +             compatible = "arm,cortex-a520-pmu";
> > > +             interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
> > > +     };
> > > +
> > > +     pmu-a720 {
> > > +             compatible = "arm,cortex-a720-pmu";
> > > +             interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
> > > +     };
> > > +
> > > +     pmu-spe {
> > > +             compatible = "arm,statistical-profiling-extension-v1";
> > > +             interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW 0>;
> > > +     };
> > 
> > SPE should follow the same model as the PMU, as each CPU has its own
> > SPE implementation, exposing different micro-architectural details.
> > 
> 
> Hi Marc,
> 
> Thanks for your reply. But there is only one compatible string
> "statistical-profiling-extension-v1" at drivers/perf/arm_spe_pmu.c,
> how could differentiate pmu-spe-a720 and pmu-spe-a520, do I need
> to change arm_spe_pmu.c as well?

I don't think there is a need to have different compatible. The driver
can probe which CPU this is on, and work out the implemented
subfeatures from the PMSIDR_EL1 register. New compatible strings are
better avoided when there is a way to probe/discover the HW (and in
most cases, there is).

Note that this equally applies to TRBE, which also explicitly deals
with interrupt partitioning and yet only has a single compatible.
Please consider adding TRBE support when you repost this series.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.