[PATCH v5 0/2] Add L1 and L2 error detection for A53 and A57

[Marc Zyngier]

On Thu, 13 Mar 2025 01:43:55 +0000,
Vijay Balakrishna <vijayb at linux.microsoft.com> wrote:
> 
> On 4/1/2021 4:06 AM, Sascha Hauer wrote:
> > Hi,
> > 
> > Resending this mainly because Marc Zyngier and Mark Rutland raised
> > concerns about using implementation defined registers and I forgot to Cc
> > them with the last version. This version, like v4 already, should fix
> > these concerns. Looking forward to feedback.
> 
> We aim to revive and adapt this patch series for A72 and A78.  Is
> anyone actively working on this?  Please share any information on why
> it wasn't pursued and thoughts on adapting it to A72 and A78.

Because, and especially for less ancient CPUs such as A78 that
implement some form of FEAT_RAS support, this makes little sense.  We
fully expect RAS errors to be handled by firmware, which knows exactly
the cache topology and can abstract the reporting into error records.
Firmware is also the correct place for all this IMPDEF stuff.

	M.

-- 
Without deviation from the norm, progress is not possible.