[PATCH net-next V2 2/2] net: axienet: Add support for 2500base-X only configuration.

[Gupta, Suraj]

[AMD Official Use Only - AMD Internal Distribution Only]

> -----Original Message-----
> From: Andrew Lunn <andrew at lunn.ch>
> Sent: Wednesday, March 12, 2025 8:29 PM
> To: Gupta, Suraj <Suraj.Gupta2 at amd.com>
> Cc: Russell King <linux at armlinux.org.uk>; Pandey, Radhey Shyam
> <radhey.shyam.pandey at amd.com>; andrew+netdev at lunn.ch;
> davem at davemloft.net; edumazet at google.com; kuba at kernel.org;
> pabeni at redhat.com; robh at kernel.org; krzk+dt at kernel.org; conor+dt at kernel.org;
> Simek, Michal <michal.simek at amd.com>; netdev at vger.kernel.org;
> devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; git (AMD-Xilinx) <git at amd.com>; Katakam, Harini
> <harini.katakam at amd.com>
> Subject: Re: [PATCH net-next V2 2/2] net: axienet: Add support for 2500base-X only
> configuration.
>
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>
> > > On Wed, Mar 12, 2025 at 02:25:27PM +0100, Andrew Lunn wrote:
> > > > > +   /* AXI 1G/2.5G ethernet IP has following synthesis options:
> > > > > +    * 1) SGMII/1000base-X only.
> > > > > +    * 2) 2500base-X only.
> > > > > +    * 3) Dynamically switching between (1) and (2), and is not
> > > > > +    * implemented in driver.
> > > > > +    */
>
> > - Keeping previous discussion short, identification of (3) depends on
> > how user implements switching logic in FPGA (external GT or RTL
> > logic). AXI 1G/2.5G IP provides only static speed selections and there
> > is no standard register to communicate that to software.
>
> So if anybody has synthesised it as 3) this change will break their system?
>
>         Andrew

It will just restrict their system to (2)