[PATCH v2 2/7] clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP

[Geert Uytterhoeven]

On Thu, 27 Feb 2025 at 13:25, John Madieu <john.madieu.xa at bp.renesas.com> wrote:
> Add required clocks and resets signals for the TSU IP available on the
> Renesas RZ/G3E SoC
>
> Signed-off-by: John Madieu <john.madieu.xa at bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>
i.e. will queue in renesas-clk for v6.15.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds