[PATCH] Remove some PMU events for FUJITSU-MONAKA

[James Clark]

On 05/03/2025 6:40 am, Yoshihiro Furudera (Fujitsu) wrote:
> Hi, James
> 
>>
>> Hi, James
>> Thank you for your comment.
>>
>>> On 27/02/2025 5:40 am, Yoshihiro Furudera wrote:
>>>> The following events are not counted properly:
>>>>
>>>> 0x0037 LL_CACHE_MISS_RD
>>>> 0x400B L3D_CACHE_LMISS_RD
>>>
>>> These two are discoverable so will still appear in
>>> /sys/bus/event_source/devices/armv8_pmuv3_0/events/ if the hardware
>>> says they exist. It might be better to change the json strings of
>>> these two to warn that they don't work if that's the case, otherwise
>>> Perf will still list them and you'll be worse off.
>>
>> I will leave these 2 events and
>> add a warning message to the description in the JSON file.
>> I will handle other events in the same way as these 2 events.
> 
> I'm thinking of adding one of the following warnings
> to the description of events where inaccurate counts
> occur on FUJITSU-MONAKA.
> Is this okay?
> 
> 1.Simple version
> "Note: This event does not count accurately."
> 
> 2.Detailed version
> "Note: This event does not count accurately because it counts as a miss regardless of whether the L3 prefetch is a hit or miss."
> 
> I think "2.Detailed version" is better.
> 
> example:
> {
>      "EventCode": "0x0396",
>      "EventName": "L2D_CACHE_REFILL_L3D_MISS",
>      "BriefDescription": "This event counts operations that cause a miss of the L3 cache. Note: This event does not count accurately because it counts as a miss regardless of whether the L3 prefetch is a hit or miss."
> }
> 
> Best Regards,
> Yoshihiro Furudera

You could have both by using BriefDescription and PublicDescription. The 
longer one being available with 'perf list -v'. I think that's what that 
feature is for.

Either way you should probably also update the description before the 
note, so add 'hit or miss' to the first sentence:

"EventCode": "0x0396",
"EventName": "L2D_CACHE_REFILL_L3D_MISS",
"BriefDescription": "This event counts operations that cause a hit or 
miss of the L3 cache. Note that this incorrectly counts both hits _and_ 
misses."