[PATCH 5/6] arm64: dts: allwinner: A523: Add thermal sensors and zones

Chen-Yu Tsai wens at csie.org
Sun Jun 29 21:45:50 PDT 2025


On Fri, Apr 11, 2025 at 8:40 AM iuncuim <iuncuim at gmail.com> wrote:
>
> From: Mikhail Kalashnikov <iuncuim at gmail.com>
>
> The A523 processor has two temperature controllers, THS0 and THS1.
> THS0 has only one temperature sensor, which is located in the DRAM.
>
> THS1 does have 3 sensors:
> ths1_0 - "big" cores
> ths1_1 - "little" cores
> ths1_2 - gpu
>
> Add the thermal sensor configuration and the thermal zones
>
> Signed-off-by: Mikhail Kalashnikov <iuncuim at gmail.com>
> ---
>  .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 138 ++++++++++++++++++
>  1 file changed, 138 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> index d626612bb..4f36032b2 100644
> --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> @@ -7,6 +7,7 @@
>  #include <dt-bindings/clock/sun55i-a523-r-ccu.h>
>  #include <dt-bindings/reset/sun55i-a523-ccu.h>
>  #include <dt-bindings/reset/sun55i-a523-r-ccu.h>
> +#include <dt-bindings/thermal/thermal.h>
>
>  / {
>         interrupt-parent = <&gic>;
> @@ -22,6 +23,7 @@ cpu0: cpu at 0 {
>                         device_type = "cpu";
>                         reg = <0x000>;
>                         enable-method = "psci";
> +                       #cooling-cells = <2>;
>                 };
>
>                 cpu1: cpu at 100 {
> @@ -29,6 +31,7 @@ cpu1: cpu at 100 {
>                         device_type = "cpu";
>                         reg = <0x100>;
>                         enable-method = "psci";
> +                       #cooling-cells = <2>;
>                 };
>
>                 cpu2: cpu at 200 {
> @@ -36,6 +39,7 @@ cpu2: cpu at 200 {
>                         device_type = "cpu";
>                         reg = <0x200>;
>                         enable-method = "psci";
> +                       #cooling-cells = <2>;
>                 };
>
>                 cpu3: cpu at 300 {
> @@ -43,6 +47,7 @@ cpu3: cpu at 300 {
>                         device_type = "cpu";
>                         reg = <0x300>;
>                         enable-method = "psci";
> +                       #cooling-cells = <2>;
>                 };
>
>                 cpu4: cpu at 400 {
> @@ -50,6 +55,7 @@ cpu4: cpu at 400 {
>                         device_type = "cpu";
>                         reg = <0x400>;
>                         enable-method = "psci";
> +                       #cooling-cells = <2>;
>                 };
>
>                 cpu5: cpu at 500 {
> @@ -57,6 +63,7 @@ cpu5: cpu at 500 {
>                         device_type = "cpu";
>                         reg = <0x500>;
>                         enable-method = "psci";
> +                       #cooling-cells = <2>;
>                 };
>
>                 cpu6: cpu at 600 {
> @@ -64,6 +71,7 @@ cpu6: cpu at 600 {
>                         device_type = "cpu";
>                         reg = <0x600>;
>                         enable-method = "psci";
> +                       #cooling-cells = <2>;
>                 };
>
>                 cpu7: cpu at 700 {
> @@ -71,6 +79,7 @@ cpu7: cpu at 700 {
>                         device_type = "cpu";
>                         reg = <0x700>;
>                         enable-method = "psci";
> +                       #cooling-cells = <2>;
>                 };
>         };
>
> @@ -171,11 +180,39 @@ ccu: clock-controller at 2001000 {
>                         #reset-cells = <1>;
>                 };
>
> +               ths1: thermal-sensor at 2009400 {
> +                       compatible = "allwinner,sun55i-a523-ths1";
> +                       reg = <0x02009400 0x400>;
> +                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC1>;
> +                       clock-names = "bus", "gpadc";
> +                       resets = <&ccu RST_BUS_THS>;
> +                       nvmem-cells = <&ths_calibration>;
> +                       nvmem-cell-names = "calibration";
> +                       #thermal-sensor-cells = <1>;
> +               };
> +
> +               ths0: thermal-sensor at 200a000 {
> +                       compatible = "allwinner,sun55i-a523-ths0";
> +                       reg = <0x0200a000 0x400>;
> +                       interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_GPADC0>;
> +                       clock-names = "bus", "gpadc";
> +                       resets = <&ccu RST_BUS_THS>;
> +                       nvmem-cells = <&ths_calibration>;
> +                       nvmem-cell-names = "calibration";
> +                       #thermal-sensor-cells = <0>;
> +               };
> +
>                 sid: efuse at 3006000 {
>                         compatible = "allwinner,sun50i-a523-sid", "allwinner,sun50i-a64-sid";
>                         reg = <0x03006000 0x1000>;
>                         #address-cells = <1>;
>                         #size-cells = <1>;
> +
> +                       ths_calibration: thermal-sensor-calibration at 38 {
> +                               reg = <0x38 0x14>;

Including unrelated bits is probably not correct. Instead I think it should
be two cells. The thermal driver then has to stitch them together or something.

> +                       };
>                 };
>
>                 mmc0: mmc at 4020000 {
> @@ -602,4 +639,105 @@ rtc: rtc at 7090000 {
>                         #clock-cells = <1>;
>                 };
>         };
> +
> +       thermal-zones {
> +               cpu0_thermal: cpu0-thermal {
> +                       polling-delay-passive = <500>;
> +                       polling-delay = <1000>;
> +                       thermal-sensors = <&ths1 1>;
> +                       sustainable-power = <1200>;

Please describe in the commit log how the sustainable power values were
derived or sourced.

> +
> +                       trips {
> +                               cpu0_threshold: cpu-trip-0 {
> +                                       temperature = <70000>;
> +                                       type = "passive";
> +                                       hysteresis = <0>;
> +                               };
> +                               cpu0_target: cpu-trip-1 {
> +                                       temperature = <90000>;
> +                                       type = "passive";
> +                                       hysteresis = <0>;
> +                               };
> +                               cpu0_critical: cpu-trip-2 {
> +                                       temperature = <110000>;
> +                                       type = "critical";
> +                                       hysteresis = <0>;
> +                               };
> +                       };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu0_target>;
> +                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +
> +               cpu4_thermal: cpu4-thermal {
> +                       polling-delay-passive = <500>;
> +                       polling-delay = <1000>;
> +                       thermal-sensors = <&ths1 0>;
> +                       sustainable-power = <1600>;
> +
> +                       trips {
> +                               cpu4_threshold: cpu-trip-0 {
> +                                       temperature = <70000>;
> +                                       type = "passive";
> +                                       hysteresis = <0>;
> +                               };
> +                               cpu4_target: cpu-trip-1 {
> +                                       temperature = <90000>;
> +                                       type = "passive";
> +                                       hysteresis = <0>;
> +                               };
> +                               cpu4_critical: cpu-trip-2 {
> +                                       temperature = <110000>;
> +                                       type = "critical";
> +                                       hysteresis = <0>;
> +                               };
> +                       };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu4_target>;
> +                                       cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +
> +               gpu-thermal {
> +                       polling-delay-passive = <500>;
> +                       polling-delay = <1000>;
> +                       thermal-sensors = <&ths1 2>;
> +                       sustainable-power = <2400>;
> +
> +                       trips {

We could have passive trip points here as well so thermal throttling of
the GPU could work.


ChenYu

> +                               gpu_temp_critical: gpu-trip-0 {
> +                                       temperature = <110000>;
> +                                       type = "critical";
> +                                       hysteresis = <0>;
> +                               };
> +                       };
> +               };
> +
> +               ddr-thermal {
> +                       polling-delay-passive = <0>;
> +                       polling-delay = <0>;
> +                       thermal-sensors = <&ths0>;
> +
> +                       trips {
> +                               ddr_temp_critical: ddr-trip-0 {
> +                                       temperature = <110000>;
> +                                       type = "critical";
> +                                       hysteresis = <0>;
> +                               };
> +                       };
> +               };
> +       };
>  };
> --
> 2.49.0
>



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