[PATCH] ARM: dts: renesas: Add boot phase tags marking to Renesas RZ/A1
Marek Vasut
marek.vasut+renesas at mailbox.org
Sun Jun 29 15:04:24 PDT 2025
bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml)
to describe various node usage during boot phases with DT. Add bootph-all for
all nodes that are used in the bootloader on Renesas RZ/A1 SoC.
All SoC require BSC bus, PFC pin control and OSTM0 timer access during all
stages of the boot process, those are marked using bootph-all property, and
so is the SoC bus node which contains the PFC and OSTM IPs.
Each board console UART is also marked as bootph-all to make it available in
all stages of the boot process.
Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
---
Cc: Conor Dooley <conor+dt at kernel.org>
Cc: Geert Uytterhoeven <geert+renesas at glider.be>
Cc: Krzysztof Kozlowski <krzk+dt at kernel.org>
Cc: Magnus Damm <magnus.damm at gmail.com>
Cc: Rob Herring <robh at kernel.org>
Cc: devicetree at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-renesas-soc at vger.kernel.org
---
arch/arm/boot/dts/renesas/r7s72100-genmai.dts | 3 ++-
arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts | 3 ++-
arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts | 2 ++
arch/arm/boot/dts/renesas/r7s72100.dtsi | 5 +++++
4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts
index c81840dfb7da..13c0324b8def 100644
--- a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts
@@ -258,6 +258,7 @@ mmcif_pins: mmcif {
};
scif2_pins: serial2 {
+ bootph-all;
/* P3_0 as TxD2; P3_2 as RxD2 */
pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
};
@@ -286,7 +287,7 @@ &rtc {
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
-
+ bootph-all;
status = "okay";
};
diff --git a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts
index 9d29861f23f1..e4f489522b2b 100644
--- a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts
+++ b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts
@@ -59,6 +59,7 @@ led1 {
&pinctrl {
scif2_pins: serial2 {
+ bootph-all;
/* P6_2 as RxD2; P6_3 as TxD2 */
pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
};
@@ -109,7 +110,7 @@ &ostm1 {
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
-
+ bootph-all;
status = "okay";
};
diff --git a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts
index 25c6d0c78828..0bf106e9827e 100644
--- a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts
@@ -199,6 +199,7 @@ keyboard_pins: keyboard {
/* Serial Console */
scif2_pins: serial2 {
+ bootph-all;
pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
<RZA1_PINMUX(3, 2, 4)>; /* RxD2 */
};
@@ -278,6 +279,7 @@ &rtc {
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
+ bootph-all;
status = "okay";
};
diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi
index 1a866dbaf5e9..c78131e3cd24 100644
--- a/arch/arm/boot/dts/renesas/r7s72100.dtsi
+++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi
@@ -41,6 +41,7 @@ bsc: bus {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x18000000>;
+ bootph-all;
};
cpus {
@@ -108,6 +109,8 @@ soc {
#size-cells = <1>;
ranges;
+ bootph-all;
+
L2: cache-controller at 3ffff000 {
compatible = "arm,pl310-cache";
reg = <0x3ffff000 0x1000>;
@@ -557,6 +560,7 @@ R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
pinctrl: pinctrl at fcfe3000 {
compatible = "renesas,r7s72100-ports";
+ bootph-all;
reg = <0xfcfe3000 0x4230>;
@@ -639,6 +643,7 @@ ostm0: timer at fcfec000 {
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
power-domains = <&cpg_clocks>;
+ bootph-all;
status = "disabled";
};
--
2.47.2
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