[PATCH v3 5/7] arm64: dts: axiado: Add initial support for AX3000 SoC and eval board

[Harshit Shah]

On 6/24/2025 11:05 PM, Krzysztof Kozlowski wrote:
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>
> On 25/06/2025 04:16, Harshit Shah wrote:
>> gpio0: gpio-controller at 80500000 {
>>                           compatible = "cdns,gpio-r1p02";
>>                           reg = <0x00 0x80500000 0x00 0x400>;
>>                           clocks = <&refclk>;
>>                           interrupt-parent = <&gic500>;
>>                           interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>>                           gpio-controller;
>>                           #gpio-cells = <2>;
>>                           interrupt-controller;
>>                           #interrupt-cells = <2>;
>>                           status = "disabled";
>>                   };
>>
>> I checked the document:
>> https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/dts-coding-style.rst#L112.
>>
>>>> +             gpio1: gpio-controller at 80580000 {
>>>> +                     compatible = "cdns,gpio-r1p02";
>>> This should not be accepted without specific compatible, but that's some
>>> old binding so maybe matters less. Anyway, if you ever need quirk or
>>> custom properties they I will reject them based on what you claim here.
>> Yes, we are not changing anything on this driver. Is it okay?
> I meant for future. I would expect to follow writing bindings now, so
> have front specific compatible, but if you do not then whatever issues
> you have in the future with this driver, they should be rejected, right?

Based on the another discussion for the UART node, we understood this 
better.

It would be better if we change this GPIO nodes to with the below 
compatible.

compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02".

>
>>
>>>
>>>> +             i3c16: i3c at 80620400 {
>>>> +                     compatible = "cdns,i3c-master";
>>>> +                     reg = <0x00 0x80620400 0x00 0x400>;
>>>> +                     clocks = <&refclk &clk_xin>;
>>>> +                     clock-names = "pclk", "sysclk";
>>>> +                     interrupt-parent = <&gic500>;
>>>> +                     interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                     i2c-scl-hz = <100000>;
>>>> +                     i3c-scl-hz = <400000>;
>>>> +                     #address-cells = <3>;
>>>> +                     #size-cells = <0>;
>>>> +                     status = "disabled";
>>>> +             };
>>>> +             uart0: serial at 80520000 {
>>> Looks like not ordered by unit address. What is the ordering rule you
>>> are going to adopt for entire arch?
>> Apologies for the confusion. I should have updated in last patch-set
>> comments.
>>
>> We are following alphabetical ordering rule. In those we are grouping
>> some nodes together based on the numbers.
>>
>> cpus
>>
>> clocks
>>
>> soc {
>>
>>      gic500 { }
>>
>>      gpio0-7 { }
>>
>>      i3c0-16 { }
>>
>>      uart0-3 { }
>>
>> }
>>
>> timer
>>
>>
>> Is this okay?
> alphabetical ordering is not mentioned in dts coding style. Maybe it
> should, but I think the only user of second style with grouping nodes -
> Renesas - still uses ordering by unit address in general.
>
> The trouble with your approach is that if you ever need to change the
> name, you will need to re-order and move entire node.
>
> Anyway, not a problem for me.

Okay, Thank you.


Regards,

Harshit.