> +&cpsw_port1 { > + status = "okay"; > + phy-mode = "rgmii-rxid"; > + phy-handle = <&cpsw3g_phy0>; Does the PCB have extra long RX clock lines? More likely, this should be 'rgmii-id', and you should delete the ti,rx-internal-delay in the PHY node, allowing it to insert the 2ns delay in the normal way. Andrew