[PATCH 2/2] ARM: dts: microchip: sama7g5: Add cache configuration for cpu node

[Mihai Sain]

Describe the cache memories according with datasheet chapter 15.2:
- L1 cache configuration with 32KB for both data and instruction cache.
- L2 cache configuration with 256KB unified cache.

Before this patch:
[    0.171425] cacheinfo: Unable to detect cache hierarchy for CPU 0

After this patch:
[root at sama7g54eb ~]$ ll -h /sys/bus/cpu/devices/cpu0/of_node/l1-cache
-r--r--r-- 1 root root 4 Jun 17 11:39 cache-level
-r--r--r-- 1 root root 0 Jun 17 11:39 cache-unified
-r--r--r-- 1 root root 6 Jun 17 11:39 compatible
-r--r--r-- 1 root root 4 Jun 17 11:39 d-cache-size
-r--r--r-- 1 root root 4 Jun 17 11:39 i-cache-size
-r--r--r-- 1 root root 9 Jun 17 11:39 name
-r--r--r-- 1 root root 4 Jun 17 11:39 next-level-cache
-r--r--r-- 1 root root 4 Jun 17 11:39 phandle

[root at sama7g54eb ~]$ ll -h /sys/bus/cpu/devices/cpu0/of_node/l2-cache
-r--r--r-- 1 root root 4 Jun 17 11:39 cache-level
-r--r--r-- 1 root root 4 Jun 17 11:39 cache-size
-r--r--r-- 1 root root 0 Jun 17 11:39 cache-unified
-r--r--r-- 1 root root 6 Jun 17 11:39 compatible
-r--r--r-- 1 root root 9 Jun 17 11:39 name
-r--r--r-- 1 root root 4 Jun 17 11:39 phandle

Signed-off-by: Mihai Sain <mihai.sain at microchip.com>
---
 arch/arm/boot/dts/microchip/sama7g5.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi
index 17bcdcf0cf4a..70175a35dc3e 100644
--- a/arch/arm/boot/dts/microchip/sama7g5.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi
@@ -38,6 +38,23 @@ cpu0: cpu at 0 {
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
+			next-level-cache = <&L1>;
+
+			L1: l1-cache {
+				compatible = "cache";
+				cache-level = <1>;
+				d-cache-size = <32768>;
+				i-cache-size = <32768>;
+				cache-unified;
+				next-level-cache = <&L2>;
+			};
+
+			L2: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-size = <262144>;
+				cache-unified;
+			};
 		};
 	};
 
-- 
2.49.0