[PATCH v1] PCI: imx6: Correct the epc feature of i.MX8M chips

[Frank Li]

On Mon, Jun 16, 2025 at 04:37:44PM +0800, Richard Zhu wrote:
> i.MX8MQ PCIes have three 64-bit BAR0/2/4 capable and programmable BARs.
> But i.MX8MM and i.MX8MP PCIes only have BAR0/BAR2 64bit programmable
> BARs, and one 256 bytes size fixed BAR4.
>
> Correct the epc featue for i.MX8MM and i.MX8MP PCIes here.

Add:

i.MX8MQ is the same as i.MX8QXP, so set i.MX8MQ's epc_features to
imx8q_pcie_epc_features.

Reviewed-by: Frank Li <Frank.Li at nxp.com>
>
> Fixes: 75c2f26da03f ("PCI: imx6: Add i.MX PCIe EP mode support")
> Signed-off-by: Richard Zhu <hongxing.zhu at nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 5a38cfaf989b..9754cc6e09b9 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -1385,6 +1385,8 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
>  	.msix_capable = false,
>  	.bar[BAR_1] = { .type = BAR_RESERVED, },
>  	.bar[BAR_3] = { .type = BAR_RESERVED, },
> +	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_256, },
> +	.bar[BAR_5] = { .type = BAR_RESERVED, },
>  	.align = SZ_64K,
>  };
>
> @@ -1912,7 +1914,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
>  		.mode_off[1] = IOMUXC_GPR12,
>  		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
> -		.epc_features = &imx8m_pcie_epc_features,
> +		.epc_features = &imx8q_pcie_epc_features,
>  		.init_phy = imx8mq_pcie_init_phy,
>  		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
>  	},
> --
> 2.37.1
>