[PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Ryan Chen]

> Subject: Re: [PATCH v0 3/5] arm64: dts: aspeed: Add initial AST2700 SoC device
> tree
> 
> On 16/06/2025 08:32, Ryan Chen wrote:
> >>>
> >>> But I don't know your previous "NAK, never tested" mean.
> >>> I did make CHECK_DTBS=y arch/arm64/boot/dts/aspeed/ don't see the
> >>> fail with
> >>> intc0: interrupt-controller at 12100000 {
> >>> 	compatible = "simple-mfd";
> >>>
> >>> So, could you point me more test instruction for this?
> >> See syscon.yaml. And writing bindings or talks on conferences:
> >> simple-mfd cannot be alone.
> >>
> >
> >         intc0: interrupt-controller at 12100000 { Sorry, do you mean add
> > by following?
> > 				 compatible = "aspeed,intc-controller", "simple-mfd";
> >  					.....
> >                  intc0_11: interrupt-controller at 1b00 {
> > 					compatible = "aspeed,ast2700-intc-ic";
> >  					......
> >                  };
> >          };
> 
> Maybe, but you said this is base address, so how can it be some separate
> device?
> 
> I mean really, don't add fake nodes just to satisfy some device instantiation.
> Describe what this really is. That is the job of DTS. Not some fake nodes.


Understood. Let me explain more about the hardware layout.
The interrupt controller space is decoded starting from 0x12100000, 
which includes both a set of global configuration registers and
individual interrupt controller instances.

The region at 0x12100000 contains global interrupt control registers
(e.g., protect config, interrupt routing etc.).

The actual interrupt controller logic starts at 0x12101b00, where each sub-controller instance
(e.g., intc0_11, intc0_12, etc.) has its own set of registers.




> 
> Best regards,
> Krzysztof